Run basic perf counting, PMI based sampling and PEBS based sampling on Intel Sapphire Rapids, Granite Rapids and Sierra Forest platforms, no issue is found. On 7/17/2025 5:03 PM, Dapeng Mi wrote: > IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[bit 17] is introduced to > indicate whether timed PEBS is supported. Timed PEBS adds a new "retired > latency" field in basic info group to show the timing info. Please find > detailed information about timed PEBS in section 8.4.1 "Timed Processor > Event Based Sampling" of "Intel Architecture Instruction Set Extensions > and Future Features". > > This patch adds PERF_CAP_PEBS_TIMING_INFO flag and KVM module leverages > this flag to expose timed PEBS feature to guest. > > Moreover, opportunistically refine the indents and make the macros > share consistent indents. > > Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx> > Tested-by: Yi Lai <yi1.lai@xxxxxxxxx> > --- > arch/x86/include/asm/msr-index.h | 14 ++++++++------ > tools/arch/x86/include/asm/msr-index.h | 14 ++++++++------ > 2 files changed, 16 insertions(+), 12 deletions(-) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index b7dded3c8113..48b7ed28718c 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -315,12 +315,14 @@ > #define PERF_CAP_PT_IDX 16 > > #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 > -#define PERF_CAP_PEBS_TRAP BIT_ULL(6) > -#define PERF_CAP_ARCH_REG BIT_ULL(7) > -#define PERF_CAP_PEBS_FORMAT 0xf00 > -#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) > -#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ > - PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) > +#define PERF_CAP_PEBS_TRAP BIT_ULL(6) > +#define PERF_CAP_ARCH_REG BIT_ULL(7) > +#define PERF_CAP_PEBS_FORMAT 0xf00 > +#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) > +#define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) > +#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ > + PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ > + PERF_CAP_PEBS_TIMING_INFO) > > #define MSR_IA32_RTIT_CTL 0x00000570 > #define RTIT_CTL_TRACEEN BIT(0) > diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h > index b7dded3c8113..48b7ed28718c 100644 > --- a/tools/arch/x86/include/asm/msr-index.h > +++ b/tools/arch/x86/include/asm/msr-index.h > @@ -315,12 +315,14 @@ > #define PERF_CAP_PT_IDX 16 > > #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 > -#define PERF_CAP_PEBS_TRAP BIT_ULL(6) > -#define PERF_CAP_ARCH_REG BIT_ULL(7) > -#define PERF_CAP_PEBS_FORMAT 0xf00 > -#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) > -#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ > - PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) > +#define PERF_CAP_PEBS_TRAP BIT_ULL(6) > +#define PERF_CAP_ARCH_REG BIT_ULL(7) > +#define PERF_CAP_PEBS_FORMAT 0xf00 > +#define PERF_CAP_PEBS_BASELINE BIT_ULL(14) > +#define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) > +#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ > + PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ > + PERF_CAP_PEBS_TIMING_INFO) > > #define MSR_IA32_RTIT_CTL 0x00000570 > #define RTIT_CTL_TRACEEN BIT(0) > > base-commit: 829f5a6308ce11c3edaa31498a825f8c41b9e9aa
