[PATCH v4 4/4] drivers: iommu: refactor arm_smmu_get_resv_regions

[Shyam Saini <shyamsaini@xxxxxxxxxxxxxxxxxxx>]

Both ARM SMMU v2/v3 drivers have common set operations for
arm_smmu_get_resv_regions(), except iommu_dma_get_resv_regions()
call all other operations can be clubed into common code block.
So to avoid code duplication put common operations in a new helper
function iommu_set_sw_msi() and call this helper function from
arm_smmu_get_resv_regions() instead.

Suggested-by: Jason Gunthorpe <jgg@xxxxxxxx>
Signed-off-by: Shyam Saini <shyamsaini@xxxxxxxxxxxxxxxxxxx>
---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 26 ++-------------
 drivers/iommu/arm/arm-smmu/arm-smmu.c       | 24 ++-----------
 drivers/iommu/iommu.c                       | 37 +++++++++++++++++++++
 include/linux/iommu.h                       |  6 ++++
 4 files changed, 47 insertions(+), 46 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 748a5513c5dbb..f4bcd2a8133b6 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -3642,32 +3642,10 @@ static int arm_smmu_of_xlate(struct device *dev,
 static void arm_smmu_get_resv_regions(struct device *dev,
 				      struct list_head *head)
 {
-	int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
-
-	static const u64 msi_bases[] = { MSI_IOVA_BASE, MSI_IOVA_BASE2 };
-
+	/* Consider reserved regions before setting MSI IOVA */
 	iommu_dma_get_resv_regions(dev, head);
 
-	/*
-	 * Use the first msi_base that does not intersect with a platform
-	 * reserved region. The SW MSI base selection is entirely arbitrary.
-	 */
-	for (int i = 0; i != ARRAY_SIZE(msi_bases); i++) {
-		struct iommu_resv_region *region;
-
-		if (resv_region_intersects(msi_bases[i], MSI_IOVA_LENGTH, head))
-			continue;
-
-		region = iommu_alloc_resv_region(msi_bases[i], MSI_IOVA_LENGTH, prot,
-						 IOMMU_RESV_SW_MSI, GFP_KERNEL);
-		if (!region) {
-			pr_warn("IOMMU: Failed to reserve MSI IOVA: No suitable MSI IOVA range available");
-			return;
-		}
-
-		list_add_tail(&region->list, head);
-		return;
-	}
+	iommu_set_sw_msi(head);
 }
 
 /*
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 84b74b8519386..2ede5d7d89a93 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -1600,30 +1600,10 @@ static int arm_smmu_of_xlate(struct device *dev,
 static void arm_smmu_get_resv_regions(struct device *dev,
 				      struct list_head *head)
 {
-	int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
-
-	static const u64 msi_bases[] = { MSI_IOVA_BASE, MSI_IOVA_BASE2 };
-
+	/* Consider reserved regions before setting MSI IOVA */
 	iommu_dma_get_resv_regions(dev, head);
 
-	/*
-	 * Use the first msi_base that does not intersect with a platform
-	 * reserved region. The SW MSI base selection is entirely arbitrary.
-	 */
-	for (int i = 0; i != ARRAY_SIZE(msi_bases); i++) {
-		struct iommu_resv_region *region;
-
-		if (resv_region_intersects(msi_bases[i], MSI_IOVA_LENGTH, head))
-			continue;
-
-		region = iommu_alloc_resv_region(msi_bases[i], MSI_IOVA_LENGTH, prot,
-						 IOMMU_RESV_SW_MSI, GFP_KERNEL);
-		if (!region)
-			return;
-
-		list_add_tail(&region->list, head);
-		return;
-	}
+	iommu_set_sw_msi(head);
 }
 
 static int arm_smmu_def_domain_type(struct device *dev)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index 060ebe330ee16..4fff01616cb5e 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -3829,3 +3829,40 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
 	return ret;
 }
 #endif /* CONFIG_IRQ_MSI_IOMMU */
+
+#if IS_ENABLED(CONFIG_IOMMU_DMA)
+/*
+ * iommu_set_sw_msi - Set up software managed MSI IOVA region
+ * @head: List of reserved IOVA regions for a device
+ *
+ * This creates a software MSI region by selecting a non-conflicting
+ * MSI_IOVA base address.
+ */
+void iommu_set_sw_msi(struct list_head *head)
+{
+	int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
+
+	static const u64 msi_bases[] = { MSI_IOVA_BASE, MSI_IOVA_BASE2 };
+
+	/*
+	 * Use the first msi_base that does not intersect with a platform
+	 * reserved region. The SW MSI base selection is entirely arbitrary.
+	 */
+	for (int i = 0; i < ARRAY_SIZE(msi_bases); i++) {
+		struct iommu_resv_region *region;
+
+		if (resv_region_intersects(msi_bases[i], MSI_IOVA_LENGTH, head))
+			continue;
+
+		region = iommu_alloc_resv_region(msi_bases[i], MSI_IOVA_LENGTH, prot,
+						 IOMMU_RESV_SW_MSI, GFP_KERNEL);
+		if (!region) {
+			pr_warn("IOMMU: Failed to reserve MSI IOVA: No suitable MSI IOVA range available");
+			return;
+		}
+
+		list_add_tail(&region->list, head);
+		return;
+	}
+}
+#endif /* CONFIG_IOMMU_DMA */
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index ce9d008b91ab5..ac1708fc20ba9 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -1558,6 +1558,8 @@ static inline void iommu_debugfs_setup(void) {}
 #define MSI_IOVA_BASE2       0xA0000000
 #define MSI_IOVA_LENGTH      0x100000
 
+void iommu_set_sw_msi(struct list_head *head);
+
 /**
  * resv_region_intersects - Check if address range overlaps with reserved regions
  * @msi_base: Start address of the range to check
@@ -1596,6 +1598,10 @@ static inline bool resv_region_intersects(phys_addr_t msi_base, size_t length,
 {
 	return false;
 }
+
+static inline void iommu_set_sw_msi(struct list_head *head)
+{
+}
 #endif	/* CONFIG_IOMMU_DMA */
 
 /*
-- 
2.34.1