On 5/13/2025 3:24 PM, H. Peter Anvin wrote:
On May 12, 2025 11:06:02 PM PDT, "Jürgen Groß" <jgross@xxxxxxxx> wrote:
On 13.05.25 07:55, Xin Li wrote:
On 5/12/2025 4:24 AM, Juergen Gross wrote:
Now with the mentioned patch really attached. :-)
Does it allow patching with an instruction more than 6 bytes long?
The immediate form MSR instructions are 9 bytes long.
Yes, shouldn't be a problem.
Juergen
However, it is more than that. The immediate instructions have a different interface, and it makes more sense to use the extra bytes to shuffle the bits around for the legacy forms:
Write:
mov %rax,%rdx
shr $32,%rdx
wrmsr(ns)
Read:
rdmsr
shl $32,%rdx
or %rdx,%rax
For the write case, this also means that two separate trap points are needed.
As far as Xen (the only user of pv msrs), note that it only paravirtualizes a very small number of MSRs, and some of those are fairly performance sensitive, so not going through the Xen framework for MSRs known to be either native or null on Xen would definitely be a win.
Hi Juergen,
I have some update on this thread while working on it.
If we continue down the path of maintaining pvops MSR APIs as this patch
series does, it seems we’ll need to duplicate the ALTERNATIVE code in
three different places.
1) The MSR access primitives defined in <asm/msr.h>, which is used when
CONFIG_PARAVIRT=n.
2) The pvops native MSR functions pv_native_{rd,wr}msr{,_safe}() defined
in arch/x86/kernel/paravirt.c, used when CONFIG_PARAVIRT=y on bare
metal.
3) The pvops Xen MSR functions paravirt_{read,write}_msr{,_safe}()
defined in <asm/paravirt.h>, used when CONFIG_PARAVIRT_XXL=y.
hpa had mentioned to me earlier that this would be a maintenance burden
— something I only truly realized once I got hands-on with it.
Maybe you have something in mind to address it?
Also add PeterZ to the To list because he cares it.
Thanks!
Xin
