On 20/02/25 09:38, Dave Hansen wrote: > But, honestly, I'm still not sure this is worth all the trouble. If > folks want to avoid IPIs for TLB flushes, there are hardware features > that *DO* that. Just get new hardware instead of adding this complicated > pile of software that we have to maintain forever. In 10 years, we'll > still have this software *and* 95% of our hardware has the hardware > feature too. Sorry, you're going to have to deal with my ignorance a little bit longer... Were you thinking x86 hardware specifically, or something else? AIUI things like arm64's TLBIVMALLE1IS can do what is required without any IPI: C5.5.78 """ The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction. """ But for (at least) these architectures: alpha x86 loongarch mips (non-freescale 8xx) powerpc riscv xtensa flush_tlb_kernel_range() has a path with a hardcoded use of on_each_cpu(), so AFAICT for these the IPIs will be sent no matter the hardware.
