On 30/08/2025 18:28, Denzeel Oliva wrote:
> Parent select bits for shared PLLs are in PLL_CON0, not PLL_CON3.
> Using the wrong register leads to incorrect parent selection and rates.
>
> Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller driver")
> Signed-off-by: Denzeel Oliva <wachiturroxd150@xxxxxxxxx>
I don't remember if I asked, but please add CC-stable in the future.
I added when applying.
Best regards,
Krzysztof
