On Mon, 25 Aug 2025 17:14:28 +0530, Ravi Patel wrote:
> Add below clock PLL support for Axis ARTPEC-8 SoC platform:
> - pll_1017x: Integer PLL with mid frequency FVCO (950 to 2400 MHz)
> This is used in ARTPEC-8 SoC for shared PLL
>
> - pll_1031x: Integer/Fractional PLL with mid frequency FVCO
> (600 to 1200 MHz)
> This is used in ARTPEC-8 SoC for Audio PLL
>
> [...]
Applied, thanks!
[02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC
https://git.kernel.org/krzk/linux/c/80770fccb7f60b0bc795852c154273e511f296a0
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
