The following changes since commit 8f5ae30d69d7543eee0d70083daf4de8fe15d585: Linux 6.17-rc1 (2025-08-10 19:41:16 +0300) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-clk-6.18 for you to fetch changes up to b3b314ef13e46dce1cdd97a856bd0250dac8feb9: clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support (2025-09-07 11:12:45 +0200) ---------------------------------------------------------------- Samsung SoC clock drivers changes for 6.18 1. Tesla FSD: Expose CSI clocks to consumers (DTS). 2. Exynos990: - Few fixes for fixed factor clocks, register widths and proper PLL parents. - Add four more clocks for the DPU and HSI0 clock for USB. - Add PERIC0 and PERIC1 clock controllers (CMU), responsible for providing clocks to serial engines. 3. Add seven clock controllers for the new Axis ARTPEC-8 SoC. The SoC shares all main blocks, including the clock controllers, with Samsung SoC, so same drivers and bindings are used. 4. Cleanups: switch to determine_rate(). ---------------------------------------------------------------- Brian Masney (2): clk: samsung: cpu: convert from round_rate() to determine_rate() clk: samsung: pll: convert from round_rate() to determine_rate() Denzeel Oliva (10): clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks dt-bindings: clock: exynos990: Extend clocks IDs clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP clk: samsung: exynos990: Add missing USB clock registers to HSI0 dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support Hakyeong Kim (3): dt-bindings: clock: Add ARTPEC-8 clock controller clk: samsung: Add clock PLL support for ARTPEC-8 SoC clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC Inbaraj E (2): dt-bindings: clock: Add CAM_CSI clock macro for FSD clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block Krzysztof Kozlowski (1): Merge branch 'for-v6.18/dt-bindings-clk' into next/clk .../bindings/clock/axis,artpec8-clock.yaml | 213 ++++ .../bindings/clock/samsung,exynos990-clock.yaml | 24 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-artpec8.c | 1044 ++++++++++++++++ drivers/clk/samsung/clk-cpu.c | 12 +- drivers/clk/samsung/clk-exynos990.c | 1240 +++++++++++++++++++- drivers/clk/samsung/clk-fsd.c | 28 +- drivers/clk/samsung/clk-pll.c | 161 ++- drivers/clk/samsung/clk-pll.h | 2 + include/dt-bindings/clock/axis,artpec8-clk.h | 169 +++ include/dt-bindings/clock/fsd-clk.h | 13 + include/dt-bindings/clock/samsung,exynos990.h | 181 +++ 12 files changed, 3032 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml create mode 100644 drivers/clk/samsung/clk-artpec8.c create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h
