On Tue, Sep 09, 2025 at 12:37:52PM +0530, Manivannan Sadhasivam wrote:
> From: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
>
> To support the DWC ECAM mechanism, prepare the driver by performing below
> configurations:
>
> 1. Since the ELBI region will be covered by the ECAM 'config' space,
> override the 'elbi_base' with the address derived from 'dbi_base' and
> the offset from PARF_SLV_DBI_ELBI register.
>
> 2. Block the transactions from the host bridge to devices other than Root
> Port on the root bus to return all F's. This is required when the 'CFG
> Shift Feature' of iATU is enabled.
FWIW, before I noticed your v9, I had updated the comments here to fix
a few inconsistencies. Here's the diff:
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 7c2b2c8c61c2..962f0311a23a 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -343,15 +343,15 @@ static void qcom_pci_config_ecam(struct dw_pcie_rp *pp)
writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);
/*
- * The only device on root bus is a single Root Port. So if PCI core
- * tries to access any devices other than Device/Function (0.0) in Bus
- * 0, the TLP will go outside of the controller to the PCI bus. But with
- * CFG Shift Feature (ECAM) enabled in iATU, there is no guarantee that
- * the response is going to be all F's. Hence, to make sure that the
+ * The only device on the root bus is a single Root Port. If we try to
+ * access any devices other than Device/Function 00.0 on Bus 0, the TLP
+ * will go outside of the controller to the PCI bus. But with CFG Shift
+ * Feature (ECAM) enabled in iATU, there is no guarantee that the
+ * response is going to be all F's. Hence, to make sure that the
* requester gets all F's response for accesses other than the Root
- * Port, configure iATU to block the transactions starting from function
- * 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb
- * to dbi_base + 1MB).
+ * Port, configure iATU to block the transactions starting from
+ * function 1 of the root bus to the end of the root bus (i.e., from
+ * dbi_base + 4KB to dbi_base + 1MB).
*/
addr = pci->dbi_phys_addr + SZ_4K;
writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE);
@@ -1385,7 +1385,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
if (pp->ecam_enabled) {
/*
* Override ELBI when ECAM is enabled, as when ECAM
- * is enabled ELBI moves along with the dbi config space.
+ * is enabled ELBI moves along with the DBI config space.
*/
offset = FIELD_GET(SLV_DBI_ELBI_ADDR_BASE, readl(pcie->parf + PARF_SLV_DBI_ELBI));
pci->elbi_base = pci->dbi_base + offset;
