On Sun, Sep 14, 2025 at 09:19:32PM +0000, Alexandru Chimac wrote: >These PLLs are found in the Exynos9610 and Exynos9810 SoCs, and >are similar to pll_1460x, so the code for that can handle this >PLL with a few small adaptations. > >Signed-off-by: Alexandru Chimac <alex@xxxxxxxxx> >--- > drivers/clk/samsung/clk-pll.c | 29 ++++++++++++++++++++++------- > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 23 insertions(+), 7 deletions(-) > >diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c >index 7bea7be1d7e45c32f0b303ffa55ce9cde4a4f71d..5fa553eab8e4b53a8854848737f619ef6a9c645a 100644 >--- a/drivers/clk/samsung/clk-pll.c >+++ b/drivers/clk/samsung/clk-pll.c >@@ -785,15 +785,20 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, > u64 fvco = parent_rate; > > pll_con0 = readl_relaxed(pll->con_reg); >- pll_con1 = readl_relaxed(pll->con_reg + 4); >- mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? >+ if (pll->type == pll_1061x) >+ pll_con1 = readl_relaxed(pll->con_reg + 12); >+ else >+ pll_con1 = readl_relaxed(pll->con_reg + 4); Nit: it would be better to use hex value for the two magic numbers. >+ mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & (((pll->type == pll_1460x) >+ || (pll->type == pll_1061x)) ? > PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); FIELD_GET is preferred. But to align the coding style, it should be fine. Regards Peng
