On Wed, Aug 6, 2025 at 2:00 AM Sangwook Shin <sw617.shin@xxxxxxxxxxx> wrote:
>
> Enable QUIRK_HAS_32BIT_CNT to ExynosAutov920 SoC which has 32-bit WTCNT.
>
> Signed-off-by: Sangwook Shin <sw617.shin@xxxxxxxxxxx>
> ---
Reviewed-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> drivers/watchdog/s3c2410_wdt.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 673ab6768688..541870b4d01a 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -357,7 +357,7 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
> .cnt_en_bit = 8,
> .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> - QUIRK_HAS_DBGACK_BIT,
> + QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_32BIT_CNT,
> };
>
> static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
> @@ -370,7 +370,7 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
> .cnt_en_bit = 8,
> .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> - QUIRK_HAS_DBGACK_BIT,
> + QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_32BIT_CNT,
> };
>
> static const struct of_device_id s3c2410_wdt_match[] = {
> --
> 2.25.1
>
