> Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC > > On 06/08/2025 10:22, Pankaj Dubey wrote: > > > > > >> -----Original Message----- > >> From: Krzysztof Kozlowski <krzk@xxxxxxxxxx> > >> Sent: Monday, July 21, 2025 12:10 PM > >> To: SeonGu Kang <ksk4725@xxxxxxxxxx>; Jesper Nilsson > >> <jesper.nilsson@xxxxxxxx>; Michael Turquette > <mturquette@xxxxxxxxxxxx>; > >> Stephen Boyd <sboyd@xxxxxxxxxx>; Rob Herring <robh@xxxxxxxxxx>; > >> Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>; Conor Dooley > >> <conor+dt@xxxxxxxxxx>; Sylwester Nawrocki > <s.nawrocki@xxxxxxxxxxx>; > >> Chanwoo Choi <cw00.choi@xxxxxxxxxxx>; Alim Akhtar > >> <alim.akhtar@xxxxxxxxxxx>; Linus Walleij <linus.walleij@xxxxxxxxxx>; > >> Tomasz Figa <tomasz.figa@xxxxxxxxx>; Catalin Marinas > >> <catalin.marinas@xxxxxxx>; Will Deacon <will@xxxxxxxxxx>; Arnd > Bergmann > >> <arnd@xxxxxxxx> > >> Cc: kenkim <kenkim@xxxxxxxxxx>; Jongshin Park <pjsin865@xxxxxxxxxx>; > >> GunWoo Kim <gwk1013@xxxxxxxxxx>; HaGyeong Kim > >> <hgkim05@xxxxxxxxxx>; GyoungBo Min <mingyoungbo@xxxxxxxxxx>; > >> SungMin Park <smn1196@xxxxxxxxxx>; Pankaj Dubey > >> <pankaj.dubey@xxxxxxxxxxx>; Shradha Todi > <shradha.t@xxxxxxxxxxx>; > >> Ravi Patel <ravi.patel@xxxxxxxxxxx>; Inbaraj E > <inbaraj.e@xxxxxxxxxxx>; > >> Swathi K S <swathi.ks@xxxxxxxxxxx>; Hrishikesh > >> <hrishikesh.d@xxxxxxxxxxx>; Dongjin Yang <dj76.yang@xxxxxxxxxxx>; > >> Sang Min Kim <hypmean.kim@xxxxxxxxxxx>; linux- > kernel@xxxxxxxxxxxxxxx; > >> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-samsung- > soc@xxxxxxxxxxxxxxx; > >> linux-arm-kernel@xxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; > >> devicetree@xxxxxxxxxxxxxxx; linux-gpio@xxxxxxxxxxxxxxx; > soc@xxxxxxxxxxxxxxx > >> Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC > >> > >> On 21/07/2025 06:50, SeonGu Kang wrote: > >>> 2025-07-10 (목), 09:07 +0200, Krzysztof Kozlowski: > >>>> On 10/07/2025 02:20, ksk4725@xxxxxxxxxx wrote: > >>>>> From: SeonGu Kang <ksk4725@xxxxxxxxxx> > >>>>> > >>>>> Add basic support for the Axis ARTPEC-8 SoC. > >>>>> This SoC contains four Cortex-A53 CPUs and other several IPs. > >>>>> > >>>>> Patches 1 to 10 provide the support for the clock controller, which > >>>>> is similar to other Samsung SoCs. > >>>>> > >>>> You should explain here (and in DTS patches or the bindings) the > >>>> hardware, that this is Samsung SoC. > >>>> > >>>> You could also explain the differences from Exynos and proposed > >>>> handling of patches (because this is odd) > >>>> > >>>> Also, entire patchset has wrong and incomplete SoBs. Your SoB is > >>>> missing everywhere, others have wrong order. > >>>> > >>>> Please read submitting patches first. > >>>> > >>> > >>> This Custom SoC is owned by the Axis (OEM) and manufactured by the > >>> Samsung (ODM). It has standard Samsung specific IP blocks. > >> > >> > >> It is designed by Samsung. It is Samsung SoC. > >> > >> Anyway, don't explain to me, but in your patchset. > > > > Hi Krzysztof, > > > > Thank you for your review comments on the ARTPEC-8 platform patches. > > I'd like to add more context about the ARTPEC-8 SoC to help clarify its > > relationship with Exynos. > > > > Here are the key details about ARTPEC-8: > > - Manufactured by Samsung Foundry > > - SoC architecture is owned by Axis Communications > > - On similar model as Tesla's FSD chip owned by Tesla and > > manufactured and by Samsung > > - IPs from both Samsung and Axis Communications > > > > Samsung-provided IPs: > > - UART > > - Ethernet (Vendor: Synopsys) > > - Same IP has been integrated as integrated in FSD Chip > > - SDIO > > - SPI > > - HSI2C > > - I2S > > - CMU (Clock Management Unit) > > Follows same CMU HW architecture as Exynos SoC have > > - Pinctrl (GPIO) > > - PCIe (Vendor: Synopsys) > > Though Exynos, FSD, ARTPEC have same DesignWare Controller, > > the glue/wrapper layer around DWC Core has differences across > > these SoCs. All manufactured by Samsung, but differences are there > > in HW design and for different products. For the same reason PCIe > patch > > refactoring effort is being put by us [1] to streamline single Exynos > driver > > which can support all Samsung manufactured SoCs having DWC PCIe > controller. > > [1]: https://protect2.fireeye.com/v1/url?k=8a8233e4-d5190ae8- > 8a83b8ab-000babff3563-7bd7c9980190e0e8&q=1&e=2e04cfd4-33cf-4f00- > a970- > 7dcbf1d780ec&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Flinu > x-pci%2Fpatch%2F20250625165229.3458-2-shradha.t%40samsung.com%2F > > So entire base of the SoC is Samsung. Yes, if we are saying this based on the core IPs (CMU, Pinctrl) and the fact that it is manufactured by Samsung. > > > > > Axis-provided IPs: > > - VIP (Image Sensor Processing IP) > > - VPP (Video Post Processing) > > - GPU > > - CDC (Video Encoder) > > > > As part of the upstreaming effort, Samsung and Coasia (DSP) team will > work together > > to upstream basic SoC support and Samsung IPs support. > > The Axis team will be the primary maintainer for the ARTPEC-8 SoC > codebase. > > Don't know what do you mean by "primary", but I want to be clear: this > classifies as Samsung SoC, so I will be maintaining and overlooking it > just like I maintain and take care about all Samsung SoCs. Otherwise you > will be introducing errors and warnings or, in best case different > style. And this already happened if I did not object! > By "primary" I mean as it is product of Axis, and only Axis will be having access to this SoCs in future they will be responsible to maintain it and add support for. > Also SAME strict DT compliance profile will be applied. (see more on > that below) > > > > > Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we believe it's > reasonable > > to create a separate directory for it, similar to FSD. > > No. It was a mistake for FSD to keep it separate why? Because there is > no single non-Samsung stuff there. I am afraid exactly the same will > happen there. > I am not sure, why you are saying this as a mistake, in case next version of FSD or ARTPEC is manufactured (ODM) by another vendor in that case, won't it create problems? For example ARTPEC-6/7 (ARM based) have their own directories as "arch/arm/boot/dts/axis/" These were not Samsung (ODM) manufactures SoCs. But ARTPEC-8/9 (ARM64) based SoCs are samsung manufactured. What if the next version say ARTPEC-10 is not samsung manufactured, so different version of products (SoCs) from same vendor (OEM), in this case Axis, will have code in separate directories and with different maintainers? > Based on above list of blocks this should be done like Google is done, > so it goes as subdirectory of samsung (exynos). Can be called axis or > artpec-8. I will suggest to keep axis, knowing the fact that sooner after artpec-8 patches gets approved and merged we have plan to upstream artpec-9 (ARM64, Samsung manufactured) as well. > > To clarify: Only this SoC, not others which are not Samsung. > > > > > We will remove Samsung and Coasia teams from the maintainers list in v2 > and only > > Axis team will be maintainer. > > A bit unexpected or rather: just use names of people who WILL be > maintaining it. If this is Jesper and Lars, great. Just don't add > entries just because they are managers. AFAIK, Jesper will be taking care. > > > > > Maintainer list for previous generation of Axis chips (ARM based) is already > present, > > so this will be merged into that. > > Existing Artpec entry does not have tree mentioned, so if you choose > above, you must not add the tree, since the tree is provided by Samsung SoC. > OK > OTOH, how are you going to add there strict DT compliance? Existing axis > is not following this, but artpec-8, as a Samsung derivative, MUST > FOLLOW strict DT compliance. And this should be clearly marked in > maintainer entry, just like everywhere else. > As I said this is tricky situation, though artpec-8 is derivative of samsung, we can't confirm if future versions (> 9) will be samsung derivative. But this would be case for all such custom ASIC manufactured by samsung, so I would like to understand how this will be handled? > > > > > Please let us know if this explanation addresses your concerns. > > We'll update the commit message and cover letter accordingly. > > > Best regards, > Krzysztof
