From: Hakyeong Kim <hgkim05@xxxxxxxxxx> Add initial clock support for ARTPEC-8 SoC which is required for enabling basic clock management. Add clock support for below CMU block in ARTPEC-8 SoC: - CMU_IMEM Signed-off-by: Ravi Patel <ravi.patel@xxxxxxxxxxx> Signed-off-by: Hakyeong Kim <hgkim05@xxxxxxxxxx> --- drivers/clk/samsung/Kconfig | 8 ++++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-artpec8.c | 62 +++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) create mode 100644 drivers/clk/samsung/clk-artpec8.c diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 76a494e95027..289591b403ad 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD + select ARTPEC8_COMMON_CLK if ARM64 && ARCH_ARTPEC8 config S3C64XX_COMMON_CLK bool "Samsung S3C64xx clock controller support" if COMPILE_TEST @@ -102,3 +103,10 @@ config TESLA_FSD_COMMON_CLK help Support for the clock controller present on the Tesla FSD SoC. Choose Y here only if you build for this SoC. + +config ARTPEC8_COMMON_CLK + bool "Axis ARTPEC-8 clock controller support" if COMPILE_TEST + depends on COMMON_CLK_SAMSUNG + help + Support for the clock controller present on the Axis ARTPEC-8 SoC. + Choose Y here only if you are building for the Axis ARTPEC-8 SoC. diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index b77fe288e4bb..473eb08fc8fc 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -3,6 +3,7 @@ # Samsung Clock specific Makefile # +obj-$(CONFIG_ARTPEC8_COMMON_CLK) += clk-artpec8.o obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) += clk-exynos3250.o obj-$(CONFIG_EXYNOS_4_COMMON_CLK) += clk-exynos4.o diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-artpec8.c new file mode 100644 index 000000000000..11a48b2fcc09 --- /dev/null +++ b/drivers/clk/samsung/clk-artpec8.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2022-2025 Axis Communications AB. + * https://www.axis.com + * + * Common Clock Framework support for ARTPEC-8 SoC. + */ + +#include <linux/clk-provider.h> +#include <dt-bindings/clock/axis,artpec8-clk.h> + +#include "clk.h" + +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CMU_IMEM_NR_CLK (MOUT_IMEM_JPEG_USER + 1) + +/* Register Offset definitions for CMU_IMEM (0x10010000) */ +#define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100 +#define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120 +#define MUX_CLK_IMEM_GIC_CA53 0x1000 +#define MUX_CLK_IMEM_GIC_CA5 0x1008 + +static const unsigned long cmu_imem_clk_regs[] __initconst = { + PLL_CON0_MUX_CLK_IMEM_ACLK_USER, + PLL_CON0_MUX_CLK_IMEM_JPEG_USER, + MUX_CLK_IMEM_GIC_CA53, + MUX_CLK_IMEM_GIC_CA5, +}; + +PNAME(mout_imem_aclk_user_p) = { "fin_pll", "dout_clkcmu_imem_aclk" }; +PNAME(mout_imem_gic_ca53_p) = { "mout_imem_aclk_user", "fin_pll" }; +PNAME(mout_imem_gic_ca5_p) = { "mout_imem_aclk_user", "fin_pll" }; +PNAME(mout_imem_jpeg_user_p) = { "fin_pll", "dout_clkcmu_imem_jpeg" }; + +static const struct samsung_mux_clock cmu_imem_mux_clks[] __initconst = { + MUX(MOUT_IMEM_ACLK_USER, "mout_imem_aclk_user", + mout_imem_aclk_user_p, PLL_CON0_MUX_CLK_IMEM_ACLK_USER, 4, 1), + MUX(MOUT_IMEM_GIC_CA53, "mout_imem_gic_ca53", + mout_imem_gic_ca53_p, MUX_CLK_IMEM_GIC_CA53, 0, 1), + MUX(MOUT_IMEM_GIC_CA5, "mout_imem_gic_ca5", + mout_imem_gic_ca5_p, MUX_CLK_IMEM_GIC_CA5, 0, 1), + MUX(MOUT_IMEM_JPEG_USER, "mout_imem_jpeg_user", + mout_imem_jpeg_user_p, PLL_CON0_MUX_CLK_IMEM_JPEG_USER, 4, 1), +}; + +static const struct samsung_cmu_info cmu_imem_info __initconst = { + .mux_clks = cmu_imem_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_imem_mux_clks), + .nr_clk_ids = CMU_IMEM_NR_CLK, + .clk_regs = cmu_imem_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_imem_clk_regs), +}; + +static void __init artpec8_clk_cmu_imem_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_imem_info); +} + +CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", + artpec8_clk_cmu_imem_init); -- 2.34.1
