From: Hakyeong Kim <hgkim05@xxxxxxxxxx> Add dt-schema for ARTPEC-8 SoC clock controller. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS - CMU_IMEM - CMU_PERI Signed-off-by: Ravi Patel <ravi.patel@xxxxxxxxxxx> Signed-off-by: Hakyeong Kim <hgkim05@xxxxxxxxxx> --- .../bindings/clock/axis,artpec8-clock.yaml | 224 ++++++++++++++++++ 1 file changed, 224 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml new file mode 100644 index 000000000000..baacea10599b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml @@ -0,0 +1,224 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC-8 SoC clock controller + +maintainers: + - Jesper Nilsson <jesper.nilsson@xxxxxxxx> + +description: | + ARTPEC-8 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that root tree + is an external clock: OSCCLK (25 MHz). This external clock must be defined + as a fixed-rate clock in dts. + + CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_CMU. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/axis,artpec8-clk.h' header. + +properties: + compatible: + enum: + - axis,artpec8-cmu-cmu + - axis,artpec8-cmu-bus + - axis,artpec8-cmu-core + - axis,artpec8-cmu-cpucl + - axis,artpec8-cmu-fsys + - axis,artpec8-cmu-imem + - axis,artpec8-cmu-peri + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-cmu + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-bus + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_BUS BUS clock (from CMU_CMU) + - description: CMU_BUS DLP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_bus_bus + - const: dout_clkcmu_bus_dlp + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CORE main clock (from CMU_CMU) + - description: CMU_CORE DLP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_core_main + - const: dout_clkcmu_core_dlp + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-cpucl + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CPUCL switch clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_cpucl_switch + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-fsys + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_FSYS SCAN0 clock (from CMU_CMU) + - description: CMU_FSYS SCAN1 clock (from CMU_CMU) + - description: CMU_FSYS BUS clock (from CMU_CMU) + - description: CMU_FSYS IP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_fsys_scan0 + - const: dout_clkcmu_fsys_scan1 + - const: dout_clkcmu_fsys_bus + - const: dout_clkcmu_fsys_ip + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-imem + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_IMEM ACLK clock (from CMU_CMU) + - description: CMU_IMEM JPEG clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_imem_aclk + - const: dout_clkcmu_imem_jpeg + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_PERI IP clock (from CMU_CMU) + - description: CMU_PERI AUDIO clock (from CMU_CMU) + - description: CMU_PERI DISP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_peri_ip + - const: dout_clkcmu_peri_audio + - const: dout_clkcmu_peri_disp + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS + - | + #include <dt-bindings/clock/axis,artpec8-clk.h> + + cmu_fsys: clock-controller@16c10000 { + compatible = "axis,artpec8-cmu-fsys"; + reg = <0x16c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN0>, + <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN1>, + <&cmu_cmu DOUT_CLKCMU_FSYS_BUS>, + <&cmu_cmu DOUT_CLKCMU_FSYS_IP>; + clock-names = "fin_pll", + "dout_clkcmu_fsys_scan0", + "dout_clkcmu_fsys_scan1", + "dout_clkcmu_fsys_bus", + "dout_clkcmu_fsys_ip"; + }; + +... -- 2.34.1
