The exynosautov920 uses v3.1 UFS device.
Add ufs node for ExynosAutov920 SoC.
And enable ufs_phy and ufs devices with ufs_fixed_vcc_reg regulator for
ExynosAutov920 SADK.
Signed-off-by: Sowon Na <sowon.na@xxxxxxxxxxx>
---
.../boot/dts/exynos/exynosautov920-sadk.dts | 17 ++++++++++++
.../arm64/boot/dts/exynos/exynosautov920.dtsi | 27 +++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
index a397f068ed53..f979cc1ae6a1 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
+++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
@@ -52,6 +52,14 @@ memory@80000000 {
<0x8 0x80000000 0x1 0xfba00000>,
<0xa 0x00000000 0x2 0x00000000>;
};
+
+ ufs_fixed_vcc_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "ufs-vcc";
+ gpio = <&gpg3 2 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ enable-active-high;
+ };
};
&pinctrl_alive {
@@ -83,6 +91,15 @@ &usi_0 {
status = "okay";
};
+&ufs_0 {
+ status = "okay";
+ vcc-supply = <&ufs_fixed_vcc_reg>;
+};
+
+&ufs_0_phy {
+ status = "okay";
+};
+
&xtcxo {
clock-frequency = <38400000>;
};
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 0fdf2062930a..f787c28fb0d5 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -1426,6 +1426,12 @@ cmu_hsi2: clock-controller@16b00000 {
"ethernet";
};
+ syscon_hsi2: syscon@16c00000 {
+ compatible = "samsung,exynosautov920-hsi2-sysreg",
+ "syscon";
+ reg = <0x16c00000 0x800>;
+ };
+
pinctrl_hsi2: pinctrl@16c10000 {
compatible = "samsung,exynosautov920-pinctrl";
reg = <0x16c10000 0x10000>;
@@ -1438,6 +1444,27 @@ pinctrl_hsi2ufs: pinctrl@16d20000 {
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
};
+ ufs_0: ufs@16e00000 {
+ compatible = "samsung,exynosautov920-ufs";
+ reg = <0x16e00000 0x100>,
+ <0x16e01100 0x400>,
+ <0x16e80000 0x8000>,
+ <0x16d08000 0x800>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_hsi2 CLK_MOUT_HSI2_UFS_EMBD_USER>,
+ <&cmu_hsi2 CLK_MOUT_HSI2_NOC_UFS_USER>;
+ clock-names = "core_clk", "sclk_unipro_main";
+ freq-table-hz = <0 0>, <0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+ phys = <&ufs_0_phy>;
+ phy-names = "ufs-phy";
+ samsung,sysreg = <&syscon_hsi2 0x710>;
+ dma-coherent;
+ status = "disabled";
+ };
+
ufs_0_phy: phy@16e04000 {
compatible = "samsung,exynosautov920-ufs-phy";
reg = <0x16e04000 0x4000>;
--
2.45.2
