> -----Original Message----- > From: Rob Herring <robh@xxxxxxxxxx> > Sent: 28 June 2025 02:43 > To: Shradha Todi <shradha.t@xxxxxxxxxxx> > Cc: linux-pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux- > samsung-soc@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-phy@xxxxxxxxxxxxxxxxxxx; linux- > fsd@xxxxxxxxx; manivannan.sadhasivam@xxxxxxxxxx; lpieralisi@xxxxxxxxxx; kw@xxxxxxxxx; > bhelgaas@xxxxxxxxxx; jingoohan1@xxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx; > alim.akhtar@xxxxxxxxxxx; vkoul@xxxxxxxxxx; kishon@xxxxxxxxxx; arnd@xxxxxxxx; > m.szyprowski@xxxxxxxxxxx; jh80.chung@xxxxxxxxxxx; pankaj.dubey@xxxxxxxxxxx > Subject: Re: [PATCH v2 06/10] dt-bindings: PCI: Add bindings support for Tesla FSD SoC > > On Wed, Jun 25, 2025 at 10:22:25PM +0530, Shradha Todi wrote: > > Document the PCIe controller device tree bindings for Tesla FSD > > SoC for both RC and EP. > > Drop 'bindings support for ' in the subject. > > > > > Signed-off-by: Shradha Todi <shradha.t@xxxxxxxxxxx> > > --- > > .../bindings/pci/samsung,exynos-pcie.yaml | 121 ++++++++++++------ > > I think this should be its own schema file. There's not much shared. > Will make 2 new bindings - samsung,exynos-pcie-common.yaml and tesla,fsd-pcie.yaml Does that sound okay? > > .../bindings/pci/tesla,fsd-pcie-ep.yaml | 91 +++++++++++++ > > 2 files changed, 176 insertions(+), 36 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml > > > > diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml > b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml > > index f20ed7e709f7..595156759b06 100644 > > --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml > > @@ -11,16 +11,15 @@ maintainers: > > - Jaehoon Chung <jh80.chung@xxxxxxxxxxx> > > > > description: |+ > > - Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare > > + Samsung SoCs PCIe host controller is based on the Synopsys DesignWare > > PCIe IP and thus inherits all the common properties defined in > > snps,dw-pcie.yaml. > > > > -allOf: > > - - $ref: /schemas/pci/snps,dw-pcie.yaml# > > - > > properties: > > compatible: > > - const: samsung,exynos5433-pcie > > + enum: > > + - samsung,exynos5433-pcie > > + - tesla,fsd-pcie > > > > reg: > > items: > > @@ -37,52 +36,102 @@ properties: > > interrupts: > > maxItems: 1 > > > > - clocks: > > - items: > > - - description: PCIe bridge clock > > - - description: PCIe bus clock > > - > > - clock-names: > > - items: > > - - const: pcie > > - - const: pcie_bus > > - > > phys: > > maxItems: 1 > > > > - vdd10-supply: > > - description: > > - Phandle to a regulator that provides 1.0V power to the PCIe block. > > - > > - vdd18-supply: > > - description: > > - Phandle to a regulator that provides 1.8V power to the PCIe block. > > - > > - num-lanes: > > - const: 1 > > - > > - num-viewport: > > - const: 3 > > - > > required: > > - reg > > - reg-names > > - interrupts > > - "#address-cells" > > - "#size-cells" > > - - "#interrupt-cells" > > - - interrupt-map > > - - interrupt-map-mask > > - ranges > > - - bus-range > > - device_type > > - num-lanes > > - - num-viewport > > - clocks > > - clock-names > > - phys > > - - vdd10-supply > > - - vdd18-supply > > + > > +allOf: > > + - $ref: /schemas/pci/snps,dw-pcie.yaml# > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - tesla,fsd-pcie > > + then: > > + properties: > > + clocks: > > + maxItems: 4 > > + > > + clock-names: > > + items: > > + - const: aux > > + - const: dbi > > + - const: mstr > > + - const: slv > > + > > + samsung,syscon-pcie: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + description: phandle for system control registers, used to > > + control signals at system level > > + > > + num-lanes: > > + maximum: 4 > > + > > + required: > > + - samsung,syscon-pcie > > + > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - samsung,exynos5433-pcie > > + then: > > + properties: > > + clocks: > > + items: > > + - description: pcie bridge clock > > + - description: pcie bus clock > > + > > + clock-names: > > + items: > > + - const: pcie > > + - const: pcie_bus > > + > > + vdd10-supply: > > + description: > > + phandle to a regulator that provides 1.0v power to the pcie block. > > + > > + vdd18-supply: > > + description: > > + phandle to a regulator that provides 1.8v power to the pcie block. > > + > > + num-lanes: > > + const: 1 > > + > > + num-viewport: > > + const: 3 > > + > > + assigned-clocks: > > + maxItems: 2 > > + > > + assigned-clock-parents: > > + maxItems: 2 > > + > > + assigned-clock-rates: > > + maxItems: 2 > > + > > + required: > > + - "#interrupt-cells" > > + - interrupt-map > > + - interrupt-map-mask > > + - bus-range > > + - num-viewport > > + - vdd10-supply > > + - vdd18-supply > > > > unevaluatedProperties: false > > > > diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml > b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml > > new file mode 100644 > > index 000000000000..f85615a0225d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml > > @@ -0,0 +1,91 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: https://protect2.fireeye.com/v1/url?k=48166268-299d775e-4817e927-74fe485fffe0- > 300a108993374478&q=1&e=3e3a0fc6-8338-4fe3-b352- > 2e510a3c6aaa&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fpci%2Ftesla%2Cfsd-pcie-ep.yaml%23 > > +$schema: https://protect2.fireeye.com/v1/url?k=60c79c47-014c8971-60c61708-74fe485fffe0- > 2608e7d54b39a025&q=1&e=3e3a0fc6-8338-4fe3-b352- > 2e510a3c6aaa&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23 > > + > > +title: Samsung SoC series PCIe Endpoint Controller > > + > > +maintainers: > > + - Shradha Todi <shradha.t@xxxxxxxxxxx> > > + > > +description: |+ > > Don't need '|+' > > > + Samsung SoCs PCIe endpoint controller is based on the Synopsys DesignWare > > + PCIe IP and thus inherits all the common properties defined in > > + snps,dw-pcie-ep.yaml. > > + > > +allOf: > > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# > > + > > +properties: > > + compatible: > > + const: tesla,fsd-pcie-ep > > + > > + reg: > > + maxItems: 4 > > + > > + reg-names: > > + items: > > + - const: elbi > > + - const: dbi > > + - const: dbi2 > > + - const: addr_space > > + > > + clocks: > > + maxItems: 4 > > + > > + clock-names: > > + items: > > + - const: aux > > + - const: dbi > > + - const: mstr > > + - const: slv > > + > > + num-lanes: > > + maximum: 4 > > + > > + samsung,syscon-pcie: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + description: phandle for system control registers, used to > > + control signals at system level > > + > > + phys: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - clocks > > + - clock-names > > + - num-lanes > > + - samsung,syscon-pcie > > + - phys > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/fsd-clk.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + bus { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + pcieep0: pcie-ep@16a00000 { > > + compatible = "tesla,fsd-pcie-ep"; > > + reg = <0x0 0x168b0000 0x0 0x1000>, > > + <0x0 0x16a00000 0x0 0x2000>, > > + <0x0 0x16a01000 0x0 0x80>, > > + <0x0 0x17000000 0x0 0xff0000>; > > + reg-names = "elbi", "dbi", "dbi2", "addr_space"; > > + clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>, > > + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>, > > + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>, > > + <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>; > > + clock-names = "aux", "dbi", "mstr", "slv"; > > + num-lanes = <4>; > > + samsung,syscon-pcie = <&sysreg_fsys1 0x50c>; > > + phys = <&pciephy1>; > > + }; > > + }; > > +... > > -- > > 2.49.0 > >
