On Fri, Jun 13, 2025 at 11:26:06AM GMT, Pritam Manohar Sutar wrote:
> This SoC has a single USB 3.1 DRD combo phy that supports both
> UTMI+ (HS) and PIPE3 (SS) and three USB2.0 DRD HS phy controllers
> those only support the UTMI+ (HS) interface.
>
> Support only UTMI+ port for this SoC which is very similar to what
> the existing Exynos850 supports.
>
> The combo phy support is out of scope of this commit.
>
> Add required change in phy driver to support HS phy for this SoC.
>
> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@xxxxxxxxxxx>
> ---
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index 917a76d584f0..15965b4c6f78 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -2025,6 +2025,28 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
> .n_regulators = ARRAY_SIZE(exynos5_regulator_names),
> };
>
> +static const struct phy_ops exynosautov920_usbdrd_phy_ops = {
> + .init = exynos850_usbdrd_phy_init,
> + .exit = exynos850_usbdrd_phy_exit,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] = {
> + {
> + .id = EXYNOS5_DRDPHY_UTMI,
> + .phy_init = exynos850_usbdrd_utmi_init,
> + },
> +};
> +
> +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = {
> + .phy_cfg = phy_cfg_exynosautov920,
> + .phy_ops = &exynosautov920_usbdrd_phy_ops,
> + .clk_names = exynos5_clk_names,
> + .n_clks = ARRAY_SIZE(exynos5_clk_names),
> + .core_clk_names = exynos5_core_clk_names,
> + .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
Where are the supplies? Where is power on/off seqequence in the phy
ops?
No pmu control (missing offset)?
You have entire commit msg to explain unusual things.
Best regards,
Krzysztof
