On 28/05/2025 12:52, Umer Uddin wrote: > The CMU_HSI1 block is used for providing clocks for the DesignWare > MMC Controller, PCIE Subsystem and UFS subsystem, and has six > dependency clocks from CMU_TOP. > > Signed-off-by: Umer Uddin <umer.uddin@xxxxxxxxxxxxxxxxxxxxxxxxxx> > --- > drivers/clk/samsung/clk-exynos990.c | 221 ++++++++++++++++++++++++++++ > 1 file changed, 221 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c > index 8d3f193d2..91ecbafcf 100644 > --- a/drivers/clk/samsung/clk-exynos990.c > +++ b/drivers/clk/samsung/clk-exynos990.c > @@ -20,6 +20,7 @@ > #define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1) > #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1) > #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1) > +#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_UFS_EMBD_USER + 1) > > /* ---- CMU_TOP ------------------------------------------------------------- */ > > @@ -1483,6 +1484,222 @@ static void __init exynos990_cmu_peris_init(struct device_node *np) > CLK_OF_DECLARE(exynos990_cmu_peris, "samsung,exynos990-cmu-peris", > exynos990_cmu_peris_init); > > +/* ---- CMU_HSI1 ------------------------------------------------------------ */ > + > +/* Register Offset definitions for CMU_HSI1 (0x13000000) */ > +#define PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER 0x0600 This is way past coding style limit: 80. This is way past hard cut-off: checkpatch. > +#define PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER 0x0604 > +#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x0610 > +#define PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x0614 > +#define PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER 0x0620 > +#define PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER 0x0624 > +#define PLL_CON0_MUX_CLKCMU_HSI1_UFS_CARD_USER 0x0630 > +#define PLL_CON1_MUX_CLKCMU_HSI1_UFS_CARD_USER 0x0634 > +#define PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER 0x0640 > +#define PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER 0x0644 > +#define HSI1_CMU_HSI1_CONTROLLER_OPTION 0x0800 > +#define CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN 0x2000 > +#define CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK 0x2008 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK 0x200c > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK 0x2010 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK 0x2014 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK 0x2018 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x201c > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2020 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK 0x2024 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK 0x2028 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK 0x202c > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2030 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL 0x2034 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK 0x2038 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_001_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x204c > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY000X2_LN07LPP_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2050 These names are not really useful. Please shorten them to 50-55 characters. > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK 0x2054 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK 0x2058 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK 0x205c > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK 0x2060 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK 0x2064 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK 0x2068 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2 0x206c > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK 0x2070 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_ACLK 0x2074 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO 0x2078 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK 0x207c > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x2080 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x2084 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x2088 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK 0x208c > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK 0x2090 > +#define CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK 0x2094 > +#define DMYQCH_CON_PCIE_GEN2_QCH_REF 0x3000 > +#define DMYQCH_CON_PCIE_GEN4_0_QCH_REF 0x3004 > +#define QCH_CON_D_TZPC_HSI1_QCH 0x3024 > +#define QCH_CON_GPIO_HSI1_QCH 0x3028 > +#define QCH_CON_HSI1_CMU_HSI1_QCH 0x302c > +#define QCH_CON_LHM_AXI_P_HSI1_QCH 0x3030 > +#define QCH_CON_LHS_ACEL_D_HSI1_QCH 0x3034 > +#define QCH_CON_MMC_CARD_QCH 0x3038 > +#define QCH_CON_PCIE_GEN2_QCH_APB 0x303c > +#define QCH_CON_PCIE_GEN2_QCH_DBI 0x3040 > +#define QCH_CON_PCIE_GEN2_QCH_MSTR Best regards, Krzysztof
