Hello Krzysztof Kozlowski, > -----Original Message----- > From: Krzysztof Kozlowski [mailto:krzk@xxxxxxxxxx] > Sent: Tuesday, April 22, 2025 5:00 PM > To: Shin Son <shin.son@xxxxxxxxxxx>; Sylwester Nawrocki > <s.nawrocki@xxxxxxxxxxx>; Chanwoo Choi <cw00.choi@xxxxxxxxxxx>; Alim > Akhtar <alim.akhtar@xxxxxxxxxxx>; Michael Turquette > <mturquette@xxxxxxxxxxxx>; Stephen Boyd <sboyd@xxxxxxxxxx>; Rob Herring > <robh@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>; Sunyeal Hong > <sunyeal.hong@xxxxxxxxxxx> > Cc: linux-samsung-soc@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx > Subject: Re: [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT > nodes > > On 18/04/2025 08:15, Shin Son wrote: > > Add cmu_cpucl0 clocks for switch, cluster, and dbg domains respectively. > > > > Signed-off-by: Shin Son <shin.son@xxxxxxxxxxx> > > --- > > arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > index fc6ac531d597..d1528633adfe 100644 > > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > @@ -582,6 +582,21 @@ pinctrl_aud: pinctrl@1a460000 { > > compatible = "samsung,exynosautov920-pinctrl"; > > reg = <0x1a460000 0x10000>; > > }; > > + > > + cmu_cpucl0: clock-controller@1ec00000 { > > + compatible = "samsung,exynosautov920-cmu-cpucl0"; > > + reg = <0x1EC00000 0x8000>; > > Lowercase hex. > > + #clock-cells = <1>; > > + > > + clocks = <&xtcxo>, > > + <&cmu_top DOUT_CLKCMU_CPUCL0_SWITCH>, > > This looks misaligned. > > > Best regards, > Krzysztof Thanks for the quick response. I'll revise everything you pointed out and send an updated patch shortly. Best regards, Shin Son
