To use the MCT as a sched_clock, the timer value has to be accessed vi an MCT register which is extremely slow. To improve performance on Arm64 SoCs, use the Arm architected timer as the default clocksource. Note, we can't completely disable the MCT on Arm64 since it needs to be used as the wakeup source for the arch_timer to exit the "c2" idle state. Since ARM SoCs don't have an architectured timer, the MCT will continue to be the default clocksource. Detailed discussion on this topic can be found at [1]. [1] https://lore.kernel.org/linux-samsung-soc/1400188079-21832-1-git-send-email-chirantan@xxxxxxxxxxxx/ Signed-off-by: Donghoon Yu <hoony.yu@xxxxxxxxxxx> Signed-off-by: Youngmin Nam <youngmin.nam@xxxxxxxxxxx> [Original commit from https://android.googlesource.com/kernel/gs/+/630817f7080e92c5e0216095ff52f6eb8dd00727 Signed-off-by: Will McVicker <willmcvicker@xxxxxxxxxx> Reviewed-by: Youngmin Nam <youngmin.nam@xxxxxxxxxxx> --- drivers/clocksource/exynos_mct.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index da09f467a6bb..96361d5dc57d 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -219,12 +219,18 @@ static struct clocksource mct_frc = { .resume = exynos4_frc_resume, }; +/* + * Since ARM devices do not have an architected timer, they need to continue + * using the MCT as the main clocksource for timekeeping, sched_clock, and the + * delay timer. For AARCH64 SoCs, the architected timer is the preferred + * clocksource due to it's superior performance. + */ +#if defined(CONFIG_ARM) static u64 notrace exynos4_read_sched_clock(void) { return exynos4_read_count_32(); } -#if defined(CONFIG_ARM) static struct delay_timer exynos4_delay_timer; static cycles_t exynos4_read_current_timer(void) @@ -250,12 +256,13 @@ static int __init exynos4_clocksource_init(bool frc_shared) exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; exynos4_delay_timer.freq = clk_rate; register_current_timer_delay(&exynos4_delay_timer); + + sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); #endif if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); - sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); return 0; } -- 2.49.0.472.ge94155a9ec-goog
