On 2025-08-26 2:11 pm, Leo Yan wrote:
On Wed, Aug 13, 2025 at 06:01:08PM +0100, Robin Murphy wrote:
Sampling is inherently a feature for CPU PMUs, given that the thing
to be sampled is a CPU context. These days, we have many more
uncore/system PMUs than CPU PMUs, so it no longer makes much sense to
assume sampling support by default and force the ever-growing majority
of drivers to opt out of it (or erroneously fail to). Instead, let's
introduce a positive opt-in capability that's more obvious and easier to
maintain.
[...]
diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index 369e77ad5f13..dbd52851f5c6 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -955,7 +955,8 @@ static int arm_spe_pmu_perf_init(struct arm_spe_pmu *spe_pmu)
spe_pmu->pmu = (struct pmu) {
.module = THIS_MODULE,
.parent = &spe_pmu->pdev->dev,
- .capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE,
+ .capabilities = PERF_PMU_CAP_SAMPLING |
+ PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE,
.attr_groups = arm_spe_pmu_attr_groups,
/*
* We hitch a ride on the software context here, so that
The change in Arm SPE driver looks good to me.
I noticed you did not set the flag for other AUX events, like Arm
CoreSight, Intel PT and bts. The drivers locate in:
drivers/hwtracing/coresight/coresight-etm-perf.c
arch/x86/events/intel/bts.c
arch/x86/events/intel/pt.c
Genearlly, AUX events generate interrupts based on AUX ring buffer
watermark but not the period. Seems to me, it is correct to set the
PERF_PMU_CAP_SAMPLING flag for them.
This cap is given to drivers which handle event->attr.sample_period and
call perf_event_overflow() - or in a few rare cases,
perf_output_sample() directly - to do something meaningful with it,
since the intent is to convey "I properly handle events for which
is_sampling_event() is true". My understanding is that aux events are
something else entirely, but I'm happy to be corrected.
Otherwise, perhaps this suggests it deserves to be named a little more
specifically for clarity, maybe PERF_CAP_SAMPLING_EVENTS?
Thanks,
Robin.
A special case is Arm CoreSight legacy sinks (like ETR/ETB, etc)
don't has interrupt. We might need set or clear the flag on the fly
based on sink type:
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index f1551c08ecb2..404edc94c198 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -433,6 +433,11 @@ static void *etm_setup_aux(struct perf_event *event, void **pages,
if (!sink)
goto err;
+ if (coresight_is_percpu_sink(sink))
+ event->pmu.capabilities = PERF_PMU_CAP_SAMPLING;
+ else
+ event->pmu.capabilities &= ~PERF_PMU_CAP_SAMPLING;
+
Thanks,
Leo
