From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Add pinctrl for SCI0 node.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
.../dts/renesas/rzt2h-n2h-evk-common.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 5f17996bcd6b..868abfdfd342 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2025 Renesas Electronics Corp.
*/
+#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
+
/ {
aliases {
serial0 = &sci0;
@@ -19,6 +21,23 @@ &extal_clk {
clock-frequency = <25000000>;
};
+&pinctrl {
+ /*
+ * SCI0 Pin Configuration:
+ * ------------------------
+ * Signal | Pin | RZ/T2H (SW4) | RZ/N2H (DSW9)
+ * -----------|---------|--------------|---------------
+ * SCI0_RXD | P27_4 | 5: ON, 6: OFF| 1: ON, 2: OFF
+ * SCI0_TXD | P27_5 | 7: ON, 8: OFF| 3: ON, 4: OFF
+ */
+ sci0_pins: sci0-pins {
+ pinmux = <RZT2H_PORT_PINMUX(27, 4, 0x14)>,
+ <RZT2H_PORT_PINMUX(27, 5, 0x14)>;
+ };
+};
+
&sci0 {
+ pinctrl-0 = <&sci0_pins>;
+ pinctrl-names = "default";
status = "okay";
};
--
2.50.1
