From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Update the rzv2h_wdt driver to make the "oscclk" clock and reset controller optional. Use devm_clk_get_optional_prepared() to obtain the "oscclk" clock, allowing the driver to work on platforms that do not provide this clock, such as the RZ/T2H SoC. Similarly, use devm_reset_control_get_optional_exclusive() to allow the driver to function on platforms that lack a reset controller. These changes are preparatory steps for supporting the RZ/T2H SoC, which does not provide an "oscclk" clock or a reset controller. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> --- v2->v3: - Merged with the patch "watchdog: rzv2h_wdt: Make reset controller optional" - Updated commit message to clarify that both "oscclk" and reset controller are made optional. - Added reviewed-by from Wolfram. v1->v2: - No changes. --- drivers/watchdog/rzv2h_wdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c index 755067800ebb..3c02960b65cf 100644 --- a/drivers/watchdog/rzv2h_wdt.c +++ b/drivers/watchdog/rzv2h_wdt.c @@ -230,11 +230,11 @@ static int rzv2h_wdt_probe(struct platform_device *pdev) if (IS_ERR(priv->pclk)) return dev_err_probe(dev, PTR_ERR(priv->pclk), "no pclk"); - priv->oscclk = devm_clk_get_prepared(dev, "oscclk"); + priv->oscclk = devm_clk_get_optional_prepared(dev, "oscclk"); if (IS_ERR(priv->oscclk)) return dev_err_probe(dev, PTR_ERR(priv->oscclk), "no oscclk"); - priv->rstc = devm_reset_control_get_exclusive(dev, NULL); + priv->rstc = devm_reset_control_get_optional_exclusive(dev, NULL); if (IS_ERR(priv->rstc)) return dev_err_probe(dev, PTR_ERR(priv->rstc), "failed to get cpg reset"); -- 2.50.1
