RE: [PATCH 1/2] clk: renesas: rzg2l: Remove DSI clock rate restrictions

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Hi Biju,

Thank you for your review!


> > +/* Required division ratio for the MIPI clock */ 
> > +int dsi_div_ab;
>
> static int dsi_div_ab;

Good catch.


> for the DPI, DIV_DSI_B = 1 and DIV_DSI_A ={2, 4, 8}
>
> So, you need to adjust the below calculation for DPI as well??

You bring up a good point.

And looking at the hardware manual again, there are other restrictions when using FOUTPOSTDIV (straight PLL) compared to FOUT1PH0 (PLL/2).


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