On 09/07/2025 15:24, Bjorn Helgaas wrote: > On Wed, Jul 09, 2025 at 08:47:05AM +0200, Krzysztof Kozlowski wrote: >> On 08/07/2025 18:34, Bjorn Helgaas wrote: >>> On Fri, Jul 04, 2025 at 07:14:04PM +0300, Claudiu wrote: >>>> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> >>>> >>>> The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express >>>> Base Specification 4.0. It is designed for root complex applications and >>>> features a single-lane (x1) implementation. Add documentation for it. >>> >>>> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml >>> >>> The "r9a08g045s33" in the filename seems oddly specific. Does it >>> leave room for descendants of the current chip that will inevitably be >>> added in the future? Most bindings are named with a fairly generic >>> family name, e.g., "fsl,layerscape", "hisilicon,kirin", "intel, >>> keembay", "samsung,exynos", etc. >>> >> >> Bindings should be named by compatible, not in a generic way, so name is >> correct. It can always grow with new compatibles even if name matches >> old one, it's not a problem. > > Ok, thanks! > > I guess that means I'm casting shade on the "r9a08g045s33" compatible. > I suppose it means something to somebody. Well, I hope it matches the name of the SoC, from which the compatible should come :) Best regards, Krzysztof
