[+cc Nam for MSI parent domain conversions, head of this thread at https://lore.kernel.org/r/20250704161410.3931884-1-claudiu.beznea.uj@xxxxxxxxxxxxxx] In subject: PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver so the important stuff is up front instead of being wrapped at the end. On Fri, Jul 04, 2025 at 07:14:05PM +0300, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > > The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express > Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions > only as a root complex, with a single-lane (x1) configuration. The > controller includes Type 1 configuration registers, as well as IP > specific registers (called AXI registers) required for various adjustments. > > Hardware manual can be downloaded from the address in the "Link" section. > The following steps should be followed to access the manual: > 1/ Click the "User Manual" button > 2/ Click "Confirm"; this will start downloading an archive > 3/ Open the downloaded archive > 4/ Navigate to r01uh1014ej*-rzg3s-users-manual-hardware -> Deliverables > 5/ Open the file r01uh1014ej*-rzg3s.pdf > > Link: https://www.renesas.com/en/products/rz-g3s?queryID=695cc067c2d89e3f271d43656ede4d12 > Tested-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > +static bool rzg3s_pcie_child_issue_request(struct rzg3s_pcie_host *host) > +{ > + u32 val; > + int ret; > + > + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_REQISS, > + RZG3S_PCI_REQISS_REQ_ISSUE, > + RZG3S_PCI_REQISS_REQ_ISSUE); > + ret = readl_poll_timeout_atomic(host->axi + RZG3S_PCI_REQISS, val, > + !(val & RZG3S_PCI_REQISS_REQ_ISSUE), > + 5, RZG3S_REQ_ISSUE_TIMEOUT_US); > + > + return !!ret || (val & RZG3S_PCI_REQISS_MOR_STATUS);
