On 19/08/2025 09:16, Ziyue Zhang wrote:
Add PCIe lane equalization preset properties with all values set to 5 for
8.0 GT/s and 16.0 GT/s data rates to enhance link stability.
Co-developed-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
Signed-off-by: Ziyue Zhang <ziyue.zhang@xxxxxxxxxxxxxxxx>
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
Acked-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 64f5378c6a47..c7a09c3605a7 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -7657,6 +7657,10 @@ pcie0: pcie@1c00000 {
phys = <&pcie0_phy>;
phy-names = "pciephy";
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+ eq-presets-16gts = /bits/ 8 <0x55 0x55>;
+
+
Please drop this empty line.
Neil
status = "disabled";
pcieport0: pcie@0 {
@@ -7827,6 +7831,9 @@ pcie1: pcie@1c10000 {
phys = <&pcie1_phy>;
phy-names = "pciephy";
+ eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
+ eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
+
status = "disabled";
pcie@0 {
