On Thu, Aug 14, 2025 at 03:02:18PM -0400, Frank Li wrote:
> On Thu, Aug 14, 2025 at 04:59:19PM +0800, Richard Zhu wrote:
> > Refer to PCIe CEM r6.0, sec 2.3 WAKE# Signal, WAKE# signal is only
> > asserted by the Add-in Card when all its functions are in D3Cold state
> > and at least one of its functions is enabled for wakeup generation.
> >
> > The 3.3V auxiliary power (+3.3Vaux) must be present and used for wakeup
> > process. Since the main power supply would be gated off to let Add-in
> > Card to be in D3Cold, add the vaux and keep it enabled to power up WAKE#
> > circuit for the entire PCIe controller lifecycle when WAKE# is supported.
>
> if it is standard, it should move to snps,dw-pcie-common.yaml.
It is standard because PCIe spec defines them. pci-bus-common.yaml
already defines these:
vpcie12v-supply:
description: 12v regulator phandle for the slot
vpcie3v3-supply:
description: 3.3v regulator phandle for the slot
vpcie3v3aux-supply:
description: 3.3v AUX regulator phandle for the slot
Note that these should really be defined in the root port node rather
than the host bridge node. We've done the latter because the RP node is
often not defined.
Rob
