Glymur is the next generation compute SoC of Qualcomm. This patch series aims to add support for the fifth PCIe instance on it. The fifth PCIe instance on Glymur has a Gen5 4-lane PHY. Patch [1/4] documents PHY as a separate compatible and Patch [2/4] documents controller as a separate compatible. Patch [3/4] describles the new PCS offsets in a dedicated header file. Patch [4/4] adds configuration and compatible for PHY. The device tree changes and whatever driver patches that are not part of this patch series will be posted separately after official announcement of the SOC. Signed-off-by: Wenbin Yao <wenbin.yao@xxxxxxxxxxxxxxxx> --- Changes in v2: - Add offsets of PLL and TXRXZ register blocks for v8.50 PHY in Patch[4/4]. - Link to v1: https://lore.kernel.org/r/20250819-glymur_pcie5-v1-0-2ea09f83cbb0@xxxxxxxxxxxxxxxx --- Prudhvi Yarlagadda (4): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY dt-bindings: PCI: qcom: Document the Glymur PCIe Controller phy: qcom-qmp: pcs: Add v8.50 register offsets phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY .../bindings/pci/qcom,pcie-x1e80100.yaml | 7 ++++- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 32 ++++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8_50.h | 13 +++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++ 5 files changed, 56 insertions(+), 1 deletion(-) --- base-commit: 886e5e7b0432360842303d587bb4a65d10741ae8 change-id: 20250818-glymur_pcie5-db4ef032e233 Best regards, -- Wenbin Yao <wenbin.yao@xxxxxxxxxxxxxxxx>
