On Fri, Aug 22, 2025 at 05:15:58PM +0800, Ziyao via B4 Relay wrote: > Older steppings of the Loongson 3C6000 series incorrectly report the > supported link speeds on their PCIe bridges (device IDs 3c19, 3c29) as > only 2.5 GT/s, despite the upstream bus supporting speeds from 2.5 GT/s > up to 16 GT/s. I assume these bridges (Root Ports?) are only found on LS3C6000 CPUs? If so, please put the quirk in arch/loongarch/pci/pci.c or drivers/pci/controller/pci-loongson.c alongside the existing fixups there. drivers/pci/quirks.c is compiled on all arches and if these bridges only exist on certain Loongson CPUs, the quirk isn't needed on other arches and wastes memory. Also, please consider adding entries for 3c19, 3c29 to the PCI IDs database: https://admin.pci-ids.ucw.cz/read/PC/0014 Thanks, Lukas
