On Wed, Aug 20 2025 at 15:54, Bjorn Helgaas wrote: > On Thu, Aug 14, 2025 at 07:28:32AM +0800, Inochi Amaoto wrote: >> As the RISC-V PLIC can not apply affinity setting without calling >> irq_enable(), it will make the interrupt unavailble when using as >> an underlying IRQ chip for MSI controller. > > s/unavailble/unavailable/ (mentioned previously) > >> Implement .irq_startup() and .irq_shutdown() for the PCI MSI and >> MSI-X templates. For chips that specify MSI_FLAG_PCI_MSI_STARTUP_PARENT, >> these startup and shutdown the parent as well, which allows the >> irq on the parent chip to be enabled if the irq is not enabled >> when allocating. This is necessary for the MSI controllers which >> use PLIC as underlying IRQ chip. > > s/irq/IRQ/ a couple times above > >> Suggested-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx> >> Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxx> > > Acked-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > > Thomas, I assume you'll merge this series; let me know if not. I'll pick it up and fixup the wording as I go.
