On 01/09/2025 07:59, Jacky Chou wrote:
> +description:
> + The ASPEED PCIe configuration syscon block provides a set of registers shared
> + by multiple PCIe-related devices within the SoC. This node represents the
> + common configuration space that allows these devices to coordinate and manage
> + shared PCIe settings, including address mapping, control, and status
> + registers. The syscon interface enables for various PCIe devices to access
> + and modify these shared registers in a consistent and centralized manner.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2700-pcie-cfg
Why this cannot be part of standard syscon binding file?
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + soc0 {
soc {
although why do you need it in the first place...
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + syscon@12c02a00 {
> + compatible = "aspeed,ast2700-pcie-cfg", "syscon";
> + reg = <0 0x12c02a00 0x80>;
> + };
> + };
Best regards,
Krzysztof
