On Mon, Aug 25, 2025 at 11:01:50PM GMT, Wenbin Yao wrote:
> From: Prudhvi Yarlagadda <quic_pyarlaga@xxxxxxxxxxx>
>
> Add support for Gen5 x4 PCIe QMP PHY found on Glymur platform.
>
> Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@xxxxxxxxxxx>
> Signed-off-by: Wenbin Yao <wenbin.yao@xxxxxxxxxxxxxxxx>
Acked-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>
- Mani
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 95830dcfdec9b1f68fd55d1cc3c102985cfafcc1..011687e6191e7a496b56cd85a149b10f7f00a749 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -93,6 +93,12 @@ static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
> };
>
> +static const unsigned int pciephy_v8_50_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_START_CTRL] = QPHY_V8_50_PCS_START_CONTROL,
> + [QPHY_PCS_STATUS] = QPHY_V8_50_PCS_STATUS1,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_50_PCS_POWER_DOWN_CONTROL,
> +};
> +
> static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
> @@ -2963,6 +2969,7 @@ struct qmp_pcie_offsets {
> u16 rx2;
> u16 txz;
> u16 rxz;
> + u16 txrxz;
> u16 ln_shrd;
> };
>
> @@ -3229,6 +3236,12 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = {
> .ln_shrd = 0x8000,
> };
>
> +static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_50 = {
> + .serdes = 0x8000,
> + .pcs = 0x9000,
> + .txrxz = 0xd000,
> +};
> +
> static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
> .lanes = 1,
>
> @@ -4258,6 +4271,22 @@ static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = {
> .phy_status = PHYSTATUS_4_20,
> };
>
> +static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = {
> + .lanes = 4,
> +
> + .offsets = &qmp_pcie_offsets_v8_50,
> +
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> +
> + .regs = pciephy_v8_50_regs_layout,
> +
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .phy_status = PHYSTATUS_4_20,
> +};
> +
> static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
> {
> const struct qmp_phy_cfg *cfg = qmp->cfg;
> @@ -5004,6 +5033,9 @@ static int qmp_pcie_probe(struct platform_device *pdev)
>
> static const struct of_device_id qmp_pcie_of_match_table[] = {
> {
> + .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy",
> + .data = &glymur_qmp_gen5x4_pciephy_cfg,
> + }, {
> .compatible = "qcom,ipq6018-qmp-pcie-phy",
> .data = &ipq6018_pciephy_cfg,
> }, {
>
> --
> 2.34.1
>
--
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