On 8/26/25 6:35 PM, Terry Bowman wrote:
> cxl_handle_rdport_cor_ras() and cxl_handle_rdport_ras() are specific
> to Restricted CXL Host (RCH) handling. Improve readability and
> maintainability by replacing these and instead using the common
> cxl_handle_cor_ras() and cxl_handle_ras() functions.
>
> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
Reviewed-by: Dave Jiang <dave.jiang@xxxxxxxxx>
>
> ---
>
> Changes in v10->v11:
> - New patch
> ---
> drivers/cxl/core/ras.c | 16 ++--------------
> 1 file changed, 2 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
> index 544a0d8773fa..0875ce8116ff 100644
> --- a/drivers/cxl/core/ras.c
> +++ b/drivers/cxl/core/ras.c
> @@ -233,12 +233,6 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)
> }
> }
>
> -static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds,
> - struct cxl_dport *dport)
> -{
> - return cxl_handle_cor_ras(cxlds, dport->regs.ras);
> -}
> -
> /*
> * Log the state of the RAS status registers and prepare them to log the
> * next error status. Return 1 if reset needed.
> @@ -276,12 +270,6 @@ static bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base)
> return true;
> }
>
> -static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds,
> - struct cxl_dport *dport)
> -{
> - return cxl_handle_ras(cxlds, dport->regs.ras);
> -}
> -
> /*
> * Copy the AER capability registers using 32 bit read accesses.
> * This is necessary because RCRB AER capability is MMIO mapped. Clear the
> @@ -350,9 +338,9 @@ static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)
>
> pci_print_aer(pdev, severity, &aer_regs);
> if (severity == AER_CORRECTABLE)
> - cxl_handle_rdport_cor_ras(cxlds, dport);
> + cxl_handle_cor_ras(cxlds, dport->regs.ras);
> else
> - cxl_handle_rdport_ras(cxlds, dport);
> + cxl_handle_ras(cxlds, dport->regs.ras);
> }
>
> void cxl_cor_error_detected(struct pci_dev *pdev)
