On Mon, Aug 11, 2025 at 09:16:37PM GMT, Shradha Todi wrote:
> Add host and endpoint controller driver support for FSD SoC.
>
Again, more info about the controller required.
> Signed-off-by: Shradha Todi <shradha.t@xxxxxxxxxxx>
> ---
> drivers/pci/controller/dwc/pci-exynos.c | 278 ++++++++++++++++++++++++
> 1 file changed, 278 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c
> index ef1f42236575..9aabfecdc147 100644
> --- a/drivers/pci/controller/dwc/pci-exynos.c
> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> @@ -18,6 +18,8 @@
> #include <linux/platform_device.h>
> #include <linux/phy/phy.h>
> #include <linux/regulator/consumer.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/mod_devicetable.h>
> #include <linux/module.h>
>
> @@ -49,15 +51,35 @@
> #define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120
> #define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
>
> +#define FSD_IRQ2_STS 0x008
> +#define FSD_IRQ_MSI_ENABLE BIT(17)
> +#define FSD_IRQ2_EN 0x018
> +#define FSD_PCIE_APP_LTSSM_ENABLE 0x054
> +#define FSD_PCIE_LTSSM_ENABLE 0x1
> +#define FSD_PCIE_DEVICE_TYPE 0x080
> +#define FSD_DEVICE_TYPE_RC 0x4
> +#define FSD_DEVICE_TYPE_EP 0x0
> +#define FSD_PCIE_CXPL_DEBUG_00_31 0x2c8
> +
> /* to store different SoC variants of Samsung */
> enum samsung_pcie_variants {
> + FSD,
> EXYNOS_5433,
I hope you are going to drop these variants and use the properties for specific
functionality as suggested by Bjorn.
> };
>
> +/* Values to be written to SYSREG to view DBI space as CDM/DBI2/IATU/DMA */
> +enum fsd_pcie_addr_type {
> + ADDR_TYPE_DBI = 0x0,
> + ADDR_TYPE_DBI2 = 0x12,
> + ADDR_TYPE_ATU = 0x36,
> + ADDR_TYPE_DMA = 0x3f,
> +};
> +
> struct samsung_pcie_pdata {
> struct pci_ops *pci_ops;
> const struct dw_pcie_ops *dwc_ops;
> const struct dw_pcie_host_ops *host_ops;
> + const struct dw_pcie_ep_ops *ep_ops;
> const struct samsung_res_ops *res_ops;
> unsigned int soc_variant;
> enum dw_pcie_device_mode device_mode;
> @@ -67,6 +89,8 @@ struct exynos_pcie {
> struct dw_pcie pci;
> void __iomem *elbi_base;
> const struct samsung_pcie_pdata *pdata;
> + struct regmap *sysreg;
> + unsigned int sysreg_offset;
> struct clk_bulk_data *clks;
> struct phy *phy;
> struct regulator_bulk_data *supplies;
> @@ -334,11 +358,201 @@ static const struct dw_pcie_ops exynos_dw_pcie_ops = {
> .start_link = exynos_pcie_start_link,
> };
>
> +static void fsd_pcie_stop_link(struct dw_pcie *pci)
> +{
> + u32 val;
> + struct exynos_pcie *ep = to_exynos_pcie(pci);
Please use reverse Xmas order for local variables.
> +
> + val = readl(ep->elbi_base + FSD_PCIE_APP_LTSSM_ENABLE);
> + val &= ~FSD_PCIE_LTSSM_ENABLE;
> + writel(val, ep->elbi_base + FSD_PCIE_APP_LTSSM_ENABLE);
> +}
> +
> +static int fsd_pcie_start_link(struct dw_pcie *pci)
> +{
> + struct exynos_pcie *ep = to_exynos_pcie(pci);
> + struct dw_pcie_ep *dw_ep = &pci->ep;
> +
> + if (dw_pcie_link_up(pci))
> + return 0;
> +
> + writel(FSD_PCIE_LTSSM_ENABLE, ep->elbi_base + FSD_PCIE_APP_LTSSM_ENABLE);
> +
> + /* no need to wait for link in case of host as core files take care */
What do you mean by 'core files'? DWC core driver?
> + if (ep->pdata->device_mode == DW_PCIE_RC_TYPE)
> + return 0;
> +
> + /* check if the link is up or not in case of EP */
> + if (!dw_pcie_wait_for_link(pci)) {
I presume there is no way to detect link up using the SPI interrupt?
> + dw_pcie_ep_linkup(dw_ep);
> + return 0;
> + }
> +
> + return -ETIMEDOUT;
> +}
> +
> +static irqreturn_t fsd_pcie_irq_handler(int irq, void *arg)
> +{
> + u32 val;
> + struct exynos_pcie *ep = arg;
> + struct dw_pcie *pci = &ep->pci;
> + struct dw_pcie_rp *pp = &pci->pp;
> +
> + val = readl(ep->elbi_base + FSD_IRQ2_STS);
> + if ((val & FSD_IRQ_MSI_ENABLE) == FSD_IRQ_MSI_ENABLE) {
> + val &= FSD_IRQ_MSI_ENABLE;
> + writel(val, ep->elbi_base + FSD_IRQ2_STS);
> + dw_handle_msi_irq(pp);
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void fsd_pcie_msi_init(struct exynos_pcie *ep)
> +{
> + int val;
> +
> + val = readl(ep->elbi_base + FSD_IRQ2_EN);
> + val |= FSD_IRQ_MSI_ENABLE;
> + writel(val, ep->elbi_base + FSD_IRQ2_EN);
Could you please explain how MSI handling works? I don't understand it.
> +}
> +
> +static void __iomem *fsd_atu_setting(struct dw_pcie *pci, void __iomem *base)
> +{
> + struct exynos_pcie *ep = to_exynos_pcie(pci);
> +
> + if (base >= pci->atu_base) {
> + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_ATU);
> + return (base - DEFAULT_DBI_ATU_OFFSET);
> + } else if (base == pci->dbi_base) {
> + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_DBI);
> + } else if (base == pci->dbi_base2) {
> + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_DBI2);
> + }
> +
> + return base;
> +}
> +
> +static u32 fsd_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size)
> +{
> + void __iomem *addr;
> + u32 val;
> +
> + addr = fsd_atu_setting(pci, base);
The returned 'addr' seems to be static. Why can't you just store it during probe
and use the 'addr' directly?
> + dw_pcie_read(addr + reg, size, &val);
> +
> + return val;
> +}
> +
> +static void fsd_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size, u32 val)
> +{
> + void __iomem *addr;
> +
> + addr = fsd_atu_setting(pci, base);
> + dw_pcie_write(addr + reg, size, val);
> +}
> +
> +static void fsd_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size, u32 val)
> +{
> + struct exynos_pcie *ep = to_exynos_pcie(pci);
> +
> + fsd_atu_setting(pci, base);
> + dw_pcie_write(pci->dbi_base + reg, size, val);
> + regmap_write(ep->sysreg, ep->sysreg_offset, ADDR_TYPE_DBI);
> +}
> +
> +static bool fsd_pcie_link_up(struct dw_pcie *pci)
> +{
> + u32 val;
> + struct exynos_pcie *ep = to_exynos_pcie(pci);
> +
> + val = readl(ep->elbi_base + FSD_PCIE_CXPL_DEBUG_00_31);
> + val &= PORT_LOGIC_LTSSM_STATE_MASK;
> +
> + return (val == PORT_LOGIC_LTSSM_STATE_L0);
> +}
> +
> +static int fsd_pcie_host_init(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct exynos_pcie *ep = to_exynos_pcie(pci);
> +
> + phy_init(ep->phy);
> + fsd_pcie_msi_init(ep);
> +
> + return 0;
> +}
> +
> +static const struct dw_pcie_host_ops fsd_pcie_host_ops = {
> + .init = fsd_pcie_host_init,
> +};
> +
> +static int fsd_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> + unsigned int type, u16 interrupt_num)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> +
> + switch (type) {
> + case PCI_IRQ_INTX:
> + return dw_pcie_ep_raise_intx_irq(ep, func_no);
> + case PCI_IRQ_MSIX:
> + dev_err(pci->dev, "EP does not support MSI-X\n");
> + return -EINVAL;
> + case PCI_IRQ_MSI:
> + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> + default:
> + dev_err(pci->dev, "UNKNOWN IRQ type\n");
Do you want to return success below even for this error?
> + }
> +
> + return 0;
this should be -EOPNOTSUPP.
> +}
> +
> +static const struct pci_epc_features fsd_pcie_epc_features = {
> + .linkup_notifier = false,
Default value is 'false'. So no need to initialize it agian.
> + .msi_capable = true,
> + .msix_capable = false,
Here also.
> +};
> +
> +static const struct pci_epc_features *fsd_pcie_get_features(struct dw_pcie_ep *ep)
> +{
> + return &fsd_pcie_epc_features;
> +}
> +
> +static const struct dw_pcie_ep_ops fsd_ep_ops = {
> + .raise_irq = fsd_pcie_raise_irq,
> + .get_features = fsd_pcie_get_features,
> +};
> +
> +static void fsd_set_device_mode(struct exynos_pcie *ep)
> +{
> + if (ep->pdata->device_mode == DW_PCIE_RC_TYPE)
> + writel(FSD_DEVICE_TYPE_RC, ep->elbi_base + FSD_PCIE_DEVICE_TYPE);
> + else
> + writel(FSD_DEVICE_TYPE_EP, ep->elbi_base + FSD_PCIE_DEVICE_TYPE);
> +}
> +
> +static const struct dw_pcie_ops fsd_dw_pcie_ops = {
> + .read_dbi = fsd_pcie_read_dbi,
> + .write_dbi = fsd_pcie_write_dbi,
> + .write_dbi2 = fsd_pcie_write_dbi2,
> + .start_link = fsd_pcie_start_link,
> + .stop_link = fsd_pcie_stop_link,
> + .link_up = fsd_pcie_link_up,
> +};
> +
> static const struct samsung_res_ops exynos_res_ops_data = {
> .init_regulator = exynos_init_regulator,
> .pcie_irq_handler = exynos_pcie_irq_handler,
> };
>
> +static const struct samsung_res_ops fsd_res_ops_data = {
> + .pcie_irq_handler = fsd_pcie_irq_handler,
> + .set_device_mode = fsd_set_device_mode,
> +};
> +
> static int exynos_pcie_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -361,6 +575,26 @@ static int exynos_pcie_probe(struct platform_device *pdev)
> if (IS_ERR(ep->phy))
> return PTR_ERR(ep->phy);
>
> + if (ep->pdata->soc_variant == FSD) {
> + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
> + if (ret)
> + return ret;
> +
> + ep->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
> + "samsung,syscon-pcie");
> + if (IS_ERR(ep->sysreg)) {
> + dev_err(dev, "sysreg regmap lookup failed.\n");
Use dev_err_probe() here and below.
> + return PTR_ERR(ep->sysreg);
> + }
> +
> + ret = of_property_read_u32_index(dev->of_node, "samsung,syscon-pcie", 1,
> + &ep->sysreg_offset);
> + if (ret) {
> + dev_err(dev, "couldn't get the register offset for syscon!\n");
> + return ret;
> + }
> + }
> +
> /* External Local Bus interface (ELBI) registers */
> ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
> if (IS_ERR(ep->elbi_base))
> @@ -397,6 +631,22 @@ static int exynos_pcie_probe(struct platform_device *pdev)
> if (ret < 0)
> goto fail_phy_init;
>
> + break;
> + case DW_PCIE_EP_TYPE:
> + phy_init(ep->phy);
> +
> + ep->pci.ep.ops = pdata->ep_ops;
> +
> + ret = dw_pcie_ep_init(&ep->pci.ep);
> + if (ret < 0)
> + goto fail_phy_init;
> +
> + ret = dw_pcie_ep_init_registers(&ep->pci.ep);
> + if (ret)
> + goto fail_phy_init;
> +
> + pci_epc_init_notify(ep->pci.ep.epc);
So the platform doesn't support PERST# and generates its own refclk?
- Mani
--
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