On Mon, Aug 11, 2025 at 09:16:38PM GMT, Shradha Todi wrote:
> Add the support for PCIe controller driver and phy driver for Tesla FSD.
> It includes support for both RC and EP.
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@xxxxxxxxxxx>
> Signed-off-by: Shradha Todi <shradha.t@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/tesla/fsd-evb.dts | 34 +++++
> arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 65 +++++++++
> arch/arm64/boot/dts/tesla/fsd.dtsi | 147 +++++++++++++++++++++
> 3 files changed, 246 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
> index 9ff22e1c8723..1b63c5d72d19 100644
> --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
> +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
> @@ -130,3 +130,37 @@ &serial_0 {
> &ufs {
> status = "okay";
> };
> +
> +&pcierc2 {
It'd be good to use underscore to differentiate RC and EP modes:
pcie_rc1
pcie_ep1
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_clkreq>, <&pcie1_wake>, <&pcie1_preset>,
> + <&pcie0_slot1>;
Could you please explain what these 'preset' and 'slot' pins are?
> +};
> +
> +&pcieep2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_clkreq>, <&pcie1_wake>, <&pcie1_preset>,
> + <&pcie0_slot1>;
> +};
> +
> +&pcierc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake0>, <&pcie0_preset0>,
> + <&pcie0_slot0>;
> +};
> +
> +&pcieep0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake0>, <&pcie0_preset0>,
> + <&pcie0_slot0>;
> +};
> +
> +&pcierc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake1>, <&pcie0_preset0>;
> +};
> +
> +&pcieep1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake1>, <&pcie0_preset0>;
> +};
[...]
> + pcieep2: pcie-ep@15400000 {
> + compatible = "tesla,fsd-pcie-ep";
> + reg = <0x0 0x15090000 0x0 0x1000>,
> + <0x0 0x15400000 0x0 0x2000>,
> + <0x0 0x15402000 0x0 0x80>,
> + <0x0 0x15800000 0x0 0xff0000>;
> + reg-names = "elbi", "dbi", "dbi2", "addr_space";
> + clocks = <&clock_fsys0 PCIE_SUBCTRL_INST0_AUX_CLK_SOC>,
> + <&clock_fsys0 PCIE_SUBCTRL_INST0_DBI_ACLK_SOC>,
> + <&clock_fsys0 PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC>,
> + <&clock_fsys0 PCIE_SUBCTRL_INST0_SLV_ACLK_SOC>;
> + clock-names = "aux", "dbi", "mstr", "slv";
> + num-lanes = <4>;
> + phys = <&pciephy0>;
> + samsung,syscon-pcie = <&sysreg_fsys0 0x434>;
> + status = "disabled";
So only host mode DMA is cache coherent and not endpoint? Weird.
- Mani
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