On Tue, 2025-09-02 at 11:09 +0200, Klaus Kudielka wrote:
> Something like this on top of mainline - completely untested, but maybe worth a try.
>
> diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
> index 755651f338..3fce4a2b63 100644
> --- a/drivers/pci/controller/pci-mvebu.c
> +++ b/drivers/pci/controller/pci-mvebu.c
> @@ -1168,9 +1168,6 @@ static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
> return devm_ioremap_resource(&pdev->dev, &port->regs);
> }
>
> -#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
> -#define DT_TYPE_IO 0x1
> -#define DT_TYPE_MEM32 0x2
> #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
> #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
>
> @@ -1189,17 +1186,9 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
> return -EINVAL;
>
> for_each_of_range(&parser, &range) {
> - unsigned long rtype;
> u32 slot = upper_32_bits(range.bus_addr);
>
> - if (DT_FLAGS_TO_TYPE(range.flags) == DT_TYPE_IO)
> - rtype = IORESOURCE_IO;
> - else if (DT_FLAGS_TO_TYPE(range.flags) == DT_TYPE_MEM32)
> - rtype = IORESOURCE_MEM;
> - else
> - continue;
> -
> - if (slot == PCI_SLOT(devfn) && type == rtype) {
> + if (slot == PCI_SLOT(devfn) && type == range.flags) {
> *tgt = DT_CPUADDR_TO_TARGET(range.cpu_addr);
> *attr = DT_CPUADDR_TO_ATTR(range.cpu_addr);
> return 0;
>
Following up myself. With this patch on top of 6.17.0-rc4, I do see the PCI bridges for the two free slots on my Turris Omnia.
One slot is occupied by mSATA. I don't have any suitable Mini-PCIe card to test, though.
$ lspci
00:02.0 PCI bridge: Marvell Technology Group Ltd. 88F6820 [Armada 385] ARM SoC (rev 04)
00:03.0 PCI bridge: Marvell Technology Group Ltd. 88F6820 [Armada 385] ARM SoC (rev 04)
$ dmesg | head -5
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 6.17.0-rc4+ (klaus@mars) (arm-linux-gnueabihf-gcc (Debian 14.3.0-5) 14.3.0, GNU ld (GNU Binutils for Debian) 2.45) #10 SMP Tue Sep 2 11:49:13 CEST 2025
[ 0.000000] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] OF: fdt: Machine model: Turris Omnia
$ dmesg | grep -i pci
[ 0.015195] PCI: CLS 0 bytes, default 64
[ 0.026199] mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
[ 0.026224] mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
[ 0.026240] mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
[ 0.026253] mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
[ 0.026265] mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
[ 0.026278] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
[ 0.026290] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
[ 0.026302] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
[ 0.026314] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
[ 0.026326] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
[ 0.026338] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
[ 0.026350] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
[ 0.026358] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
[ 0.026554] mvebu-pcie soc:pcie: pcie1.0: Slot power limit 10.0W
[ 0.026743] mvebu-pcie soc:pcie: pcie2.0: Slot power limit 10.0W
[ 0.026955] mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
[ 0.026963] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 0.026970] pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address [0x00080000-0x00081fff])
[ 0.026976] pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address [0x00040000-0x00041fff])
[ 0.026981] pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address [0x00044000-0x00045fff])
[ 0.026986] pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address [0x00048000-0x00049fff])
[ 0.026991] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
[ 0.026995] pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
[ 0.027113] pci 0000:00:02.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
[ 0.027127] pci 0000:00:02.0: PCI bridge to [bus 00]
[ 0.027134] pci 0000:00:02.0: bridge window [io 0x0000-0x0fff]
[ 0.027138] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff]
[ 0.027277] /soc/pcie/pcie@2,0: Fixed dependency cycle(s) with /soc/pcie/pcie@2,0/interrupt-controller
[ 0.027311] pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
[ 0.027323] pci 0000:00:03.0: PCI bridge to [bus 00]
[ 0.027329] pci 0000:00:03.0: bridge window [io 0x0000-0x0fff]
[ 0.027333] pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff]
[ 0.027443] /soc/pcie/pcie@3,0: Fixed dependency cycle(s) with /soc/pcie/pcie@3,0/interrupt-controller
[ 0.028311] PCI: bus0: Fast back to back transfers disabled
[ 0.028319] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 0.028327] pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 0.028418] PCI: bus1: Fast back to back transfers enabled
[ 0.028424] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 0.028506] PCI: bus2: Fast back to back transfers enabled
[ 0.028510] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
[ 0.028526] pci 0000:00:02.0: PCI bridge to [bus 01]
[ 0.028535] pci 0000:00:03.0: PCI bridge to [bus 02]
[ 0.028542] pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
[ 0.028547] pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
[ 0.028552] pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
[ 0.028556] pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
[ 0.028560] pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
[ 0.028564] pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
