On Fri, Jun 20, 2025 at 11:55:06PM +0800, Hans Zhang wrote: > Current PCIe initialization logic may leave root ports operating with > non-optimal Maximum Payload Size (MPS) settings. While downstream device > configuration is handled during bus enumeration, root port MPS values > inherited from firmware or hardware defaults ... Apparently Root Port MPS configuration is different from that for downstream devices? > might not utilize the full > capabilities supported by the controller hardware. This can result in > suboptimal data transfer efficiency across the PCIe hierarchy. > > During host controller probing phase, when PCIe bus tuning is enabled, > the implementation now configures root port MPS settings to their > hardware-supported maximum values. Specifically, when configuring the MPS > for a PCIe device, if the device is a root port and the bus tuning is not > disabled (PCIE_BUS_TUNE_OFF), the MPS is set to 128 << dev->pcie_mpss to > match the Root Port's maximum supported payload size. The Max Read Request > Size (MRRS) is subsequently adjusted through existing companion logic to > maintain compatibility with PCIe specifications. > > Note that this initial setting of the root port MPS to the maximum might > be reduced later during the enumeration of downstream devices if any of > those devices do not support the maximum MPS of the root port. > > Explicit initialization at host probing stage ensures consistent PCIe > topology configuration before downstream devices perform their own MPS > negotiations. This proactive approach addresses platform-specific > requirements where controller drivers depend on properly initialized > root port settings, while maintaining backward compatibility through > PCIE_BUS_TUNE_OFF conditional checks. Hardware capabilities are fully > utilized without altering existing device negotiation behaviors. This last paragraph seems kind of like marketing without any real content. Is there something important in there? Nits: s/root port/Root Port/ Reword "implementation now configures" to be clear about whether "now" refers to before this patch or after. Update the MRRS "to maintain compatibility" part. I'm dubious about there being a spec compatibility issue with respect to MRRS. Cite the relevant section if there is an issue. > Suggested-by: Niklas Cassel <cassel@xxxxxxxxxx> > Suggested-by: Manivannan Sadhasivam <mani@xxxxxxxxxx> > Signed-off-by: Hans Zhang <18255117159@xxxxxxx> > --- > drivers/pci/probe.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index 4b8693ec9e4c..9f8803da914c 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -2178,6 +2178,16 @@ static void pci_configure_mps(struct pci_dev *dev) > return; > } > > + /* > + * Unless MPS strategy is PCIE_BUS_TUNE_OFF (don't touch MPS at all), > + * start off by setting root ports' MPS to MPSS. Depending on the MPS > + * strategy, and the MPSS of the devices below the root port, the MPS > + * of the root port might get overridden later. > + */ > + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT && > + pcie_bus_config != PCIE_BUS_TUNE_OFF) > + pcie_set_mps(dev, 128 << dev->pcie_mpss); > + > if (!bridge || !pci_is_pcie(bridge)) > return; > > -- > 2.25.1 >
