On Mon, 08 Sep 2025 17:38:27 +0530, Siddharth Vadapalli wrote:
> The Cadence PCIe Controller integrated in the TI K3 SoCs supports both
> Root-Complex and Endpoint modes of operation. The Glue Layer allows
> "strapping" the Mode of operation of the Controller, the Link Speed
> and the Link Width. This is enabled by programming the "PCIEn_CTRL"
> register (n corresponds to the PCIe instance) within the CTRL_MMR
> memory-mapped register space. The "reset-values" of the registers are
> also different depending on the mode of operation.
>
> [...]
Applied, thanks!
[1/1] PCI: j721e: Fix programming sequence of "strap" settings
commit: f842d3313ba179d4005096357289c7ad09cec575
Best regards,
--
Manivannan Sadhasivam <mani@xxxxxxxxxx>
