On Mon, Sep 08, 2025 at 11:36:02AM +0530, Manivannan Sadhasivam wrote:
> On Wed, Aug 20, 2025 at 04:10:48PM GMT, Richard Zhu wrote:
> > The CLKREQ# is an open drain, active low signal that is driven low by
> > the card to request reference clock.
> >
> > Since the reference clock may be required by i.MX PCIe host too.
>
> Add some info on why the refclk is needed by the host.
>
> > To make
> > sure this clock is available even when the CLKREQ# isn't driven low by
> > the card(e.x no card connected), force CLKREQ# override active low for
> > i.MX PCIe host during initialization.
> >
>
> CLKREQ# override is not a spec defined feature. So you need to explain what it
> does first.
>
> > The CLKREQ# override can be cleared safely when supports-clkreq is
> > present and PCIe link is up later. Because the CLKREQ# would be driven
> > low by the card in this case.
> >
>
> Why do you need to depend on 'supports-clkreq' property? Don't you already know
> if your platform supports CLKREQ# or not? None of the upstream DTS has the
> 'supports-clkreq' property set and the NXP binding also doesn't enable this
> property.
It is history reason. Supposed all the boards which supports L1SS need set
'supports-clkreq' in dts. L1SS require board design use open drain connect
RC's clk-req and EP's clk-req together, which come from one ECN of PCI
spec.
But most M.2 slot now, which support L1SS, so most platform default enable
L1SS or default 'supports-clkreq' on.
Ideally, 'supports-clkreq' should use revert logic like 'clk-req-broken'.
but 'supports-clkreq' already come into stardard PCIe binding now.
One of i.MX95 boards use standard PCIe slot, PIN 12
12 CLKREQ# Ground Clock Request Signal[26]
which is reserved at old PCIe standard, so some old PCIe card float this
pin.
So I think most dts in kernel tree should add 'supports-clkreq' property
if they use M.2 and connect CLK_REQ# as below [1]
============================================
VCC
---
|
R (10K)
|
CLK_REQ# (RC)------ CLK_REQ#(EP)
NOT add supports-clkreq if connect as below [2]
==========================================
CLK_REQ# (RC) ---> |---------|
| OR GATE | ---> control ref clock
CLK_REQ#(EP) ---> |-------- |
>
> So I'm wondering how you are suddenly using this property. The property implies
> that when not set to true, CLKREQ# is not supported by the platform. So when the
> driver starts using this property, all the old DTS based platforms are not going
> to release CLKREQ# from driving low, so L1SS will not be entered for them. Do
> you really want it to happen?
Actually, some old board use [2]. we will add supports-clkreq if board
design use [1], so correct reflect board design.
Frank
>
> - Mani
>
> > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++
> > 1 file changed, 35 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index 80e48746bbaf6..a73632b47e2d3 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -52,6 +52,8 @@
> > #define IMX95_PCIE_REF_CLKEN BIT(23)
> > #define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9)
> > #define IMX95_PCIE_SS_RW_REG_1 0xf4
> > +#define IMX95_PCIE_CLKREQ_OVERRIDE_EN BIT(8)
> > +#define IMX95_PCIE_CLKREQ_OVERRIDE_VAL BIT(9)
> > #define IMX95_PCIE_SYS_AUX_PWR_DET BIT(31)
> >
> > #define IMX95_PE0_GEN_CTRL_1 0x1050
> > @@ -136,6 +138,7 @@ struct imx_pcie_drvdata {
> > int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
> > int (*core_reset)(struct imx_pcie *pcie, bool assert);
> > int (*wait_pll_lock)(struct imx_pcie *pcie);
> > + void (*clr_clkreq_override)(struct imx_pcie *pcie);
> > const struct dw_pcie_host_ops *ops;
> > };
> >
> > @@ -149,6 +152,7 @@ struct imx_pcie {
> > struct gpio_desc *reset_gpiod;
> > struct clk_bulk_data *clks;
> > int num_clks;
> > + bool supports_clkreq;
> > struct regmap *iomuxc_gpr;
> > u16 msi_ctrl;
> > u32 controller_id;
> > @@ -267,6 +271,13 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
> > IMX95_PCIE_REF_CLKEN,
> > IMX95_PCIE_REF_CLKEN);
> >
> > + /* Force CLKREQ# low by override */
> > + regmap_update_bits(imx_pcie->iomuxc_gpr,
> > + IMX95_PCIE_SS_RW_REG_1,
> > + IMX95_PCIE_CLKREQ_OVERRIDE_EN |
> > + IMX95_PCIE_CLKREQ_OVERRIDE_VAL,
> > + IMX95_PCIE_CLKREQ_OVERRIDE_EN |
> > + IMX95_PCIE_CLKREQ_OVERRIDE_VAL);
> > return 0;
> > }
> >
> > @@ -1298,6 +1309,18 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
> > regulator_disable(imx_pcie->vpcie);
> > }
> >
> > +static void imx8mm_pcie_clr_clkreq_override(struct imx_pcie *imx_pcie)
> > +{
> > + imx8mm_pcie_enable_ref_clk(imx_pcie, false);
> > +}
> > +
> > +static void imx95_pcie_clr_clkreq_override(struct imx_pcie *imx_pcie)
> > +{
> > + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
> > + IMX95_PCIE_CLKREQ_OVERRIDE_EN |
> > + IMX95_PCIE_CLKREQ_OVERRIDE_VAL, 0);
> > +}
> > +
> > static void imx_pcie_host_post_init(struct dw_pcie_rp *pp)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > @@ -1322,6 +1345,12 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp)
> > dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
> > dw_pcie_dbi_ro_wr_dis(pci);
> > }
> > +
> > + /* Clear CLKREQ# override if supports_clkreq is true and link is up */
> > + if (dw_pcie_link_up(pci) && imx_pcie->supports_clkreq) {
> > + if (imx_pcie->drvdata->clr_clkreq_override)
> > + imx_pcie->drvdata->clr_clkreq_override(imx_pcie);
> > + }
> > }
> >
> > /*
> > @@ -1745,6 +1774,8 @@ static int imx_pcie_probe(struct platform_device *pdev)
> > pci->max_link_speed = 1;
> > of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
> >
> > + imx_pcie->supports_clkreq =
> > + of_property_read_bool(node, "supports-clkreq");
> > imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
> > if (IS_ERR(imx_pcie->vpcie)) {
> > if (PTR_ERR(imx_pcie->vpcie) != -ENODEV)
> > @@ -1873,6 +1904,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> > .init_phy = imx8mq_pcie_init_phy,
> > .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> > + .clr_clkreq_override = imx8mm_pcie_clr_clkreq_override,
> > },
> > [IMX8MM] = {
> > .variant = IMX8MM,
> > @@ -1883,6 +1915,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > .mode_off[0] = IOMUXC_GPR12,
> > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> > + .clr_clkreq_override = imx8mm_pcie_clr_clkreq_override,
> > },
> > [IMX8MP] = {
> > .variant = IMX8MP,
> > @@ -1893,6 +1926,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > .mode_off[0] = IOMUXC_GPR12,
> > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
> > .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> > + .clr_clkreq_override = imx8mm_pcie_clr_clkreq_override,
> > },
> > [IMX8Q] = {
> > .variant = IMX8Q,
> > @@ -1913,6 +1947,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> > .core_reset = imx95_pcie_core_reset,
> > .init_phy = imx95_pcie_init_phy,
> > .wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
> > + .clr_clkreq_override = imx95_pcie_clr_clkreq_override,
> > },
> > [IMX8MQ_EP] = {
> > .variant = IMX8MQ_EP,
> > --
> > 2.37.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
