On 9/5/25 2:06 PM, Jason Gunthorpe wrote:
This brings the definitions up to PCI Express revision 5.0:
* ACS I/O Request Blocking Enable
* ACS DSP Memory Target Access Control
* ACS USP Memory Target Access Control
* ACS Unclaimed Request Redirect
Support for this entire grouping is advertised by the ACS Enhanced
Capability bit.
Signed-off-by: Jason Gunthorpe <jgg@xxxxxxxxxx>
---
include/uapi/linux/pci_regs.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 6095e7d7d4cc48..54621e6e83572e 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1005,8 +1005,16 @@
#define PCI_ACS_UF 0x0010 /* Upstream Forwarding */
#define PCI_ACS_EC 0x0020 /* P2P Egress Control */
#define PCI_ACS_DT 0x0040 /* Direct Translated P2P */
+#define PCI_ACS_ENHANCED 0x0080 /* IORB, DSP_MT_xx, USP_MT_XX. Capability only */
+#define PCI_ACS_EGRESS_CTL_SZ GENMASK(15, 8) /* Egress Control Vector Size */
#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
+#define PCI_ACS_IORB 0x0080 /* I/O Request Blocking */
+#define PCI_ACS_DSP_MT_RB 0x0100 /* DSP Memory Target Access Control Request Blocking */
+#define PCI_ACS_DSP_MT_RR 0x0200 /* DSP Memory Target Access Control Request Redirect */
+#define PCI_ACS_USP_MT_RB 0x0400 /* USP Memory Target Access Control Request Blocking */
+#define PCI_ACS_USP_MT_RR 0x0800 /* USP Memory Target Access Control Request Redirect */
+#define PCI_ACS_UNCLAIMED_RR 0x1000 /* Unclaimed Request Redirect Control */
#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
/*
Reviewed-by: Donald Dutile <ddutile@xxxxxxxxxx>
