On 8/28/2025 3:18 AM, Alejandro Lucero Palau wrote:
> Hi Terry,
>
>
> On 8/27/25 02:35, Terry Bowman wrote:
>> CXL and AER drivers need the ability to identify CXL devices.
>>
>> Introduce set_pcie_cxl() with logic checking for CXL.mem or CXL.cache
>> status in the CXL Flexbus DVSEC status register. The CXL Flexbus DVSEC
>> presence is used because it is required for all the CXL PCIe devices.[1]
>>
>> Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL
>> CXL.cache and CXl.mem status.
>>
>> In the case the device is an EP or USP, call set_pcie_cxl() on behalf of
>> the parent downstream device. This will make certain the correct state
>> is cached.
>>
>> Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'.
>>
>> [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended
>> Capability (DVSEC) ID Assignment, Table 8-2
>>
>> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
>> Reviewed-by: Ira Weiny <ira.weiny@xxxxxxxxx>
>> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@xxxxxxxxxxxxxxx>
>> Reviewed-by: Dave Jiang <dave.jiang@xxxxxxxxx>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
>
> With the changes for checking flexbus state:
>
>
> Reviewed-by: Alejandro Lucero <alucerop@xxxxxxx>
>
Thanks Alejandro.
> Just a minor thing below, something I do not fully understand but I
> guess it was discussed/explained previously.
>
>
>> ---
>> Changes in v10->v11:
>> - Amended set_pcie_cxl() to check for Upstream Port's and EP's parent
>> downstream port by calling set_pcie_cxl(). (Dan)
>> - Retitle patch: 'Add' -> 'Introduce'
>> - Add check for CXL.mem and CXL.cache (Alejandro, Dan)
>> ---
>> drivers/pci/probe.c | 25 +++++++++++++++++++++++++
>> include/linux/pci.h | 6 ++++++
>> include/uapi/linux/pci_regs.h | 3 +++
>> 3 files changed, 34 insertions(+)
>>
>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
>> index 4b8693ec9e4c..b08cd0346136 100644
>> --- a/drivers/pci/probe.c
>> +++ b/drivers/pci/probe.c
>> @@ -1691,6 +1691,29 @@ static void set_pcie_thunderbolt(struct pci_dev *dev)
>> dev->is_thunderbolt = 1;
>> }
>>
>> +static void set_pcie_cxl(struct pci_dev *dev)
>> +{
>> + struct pci_dev *parent;
>> + u16 dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL,
>> + PCI_DVSEC_CXL_FLEXBUS_PORT);
>> + if (dvsec) {
>> + u16 cap;
>> +
>> + pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_FLEXBUS_STATUS_OFFSET, &cap);
>> +
>> + dev->is_cxl = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_STATUS_CACHE_MASK, cap) ||
>> + FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_STATUS_MEM_MASK, cap);
>> + }
>> +
>> + if (!pci_is_pcie(dev) ||
>> + !(pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
>> + pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM))
>> + return;
>> +
>> + parent = pci_upstream_bridge(dev);
>> + set_pcie_cxl(parent);
>
> This recursion is confusing to me.
>
> Is it not the parent already having this set from its own pci setup? Or
> maybe do we expect that to change after a reset and this is a sanity check?
>
Right. The upstream parent bus state is already set but could change after reset.
Terry
