Hi Yao Zi,
On 9/6/2025 3:52 PM, Yao Zi wrote:
> Describes the PCIe Gen2x1 controller integrated in RK3528 SoC. The SoC
> doesn't provide a separate MSI controller, thus the one integrated in
> designware PCIe IP must be used.
>
> Signed-off-by: Yao Zi <ziyao@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/rockchip/rk3528.dtsi | 56 +++++++++++++++++++++++-
> 1 file changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> index db5dbcac7756..2d2af467e5ab 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> #include <dt-bindings/clock/rockchip,rk3528-cru.h>
> #include <dt-bindings/power/rockchip,rk3528-power.h>
> @@ -239,7 +240,7 @@ gmac0_clk: clock-gmac50m {
>
> soc {
> compatible = "simple-bus";
> - ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
> + ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44400000>;
We should use the dbi reg area in the 32-bit address space, please use:
ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x4000000>;
> #address-cells = <2>;
> #size-cells = <2>;
>
> @@ -1133,6 +1134,59 @@ combphy: phy@ffdc0000 {
> rockchip,pipe-phy-grf = <&pipe_phy_grf>;
> status = "disabled";
> };
> +
> + pcie: pcie@fe4f0000 {
With the dbi reg area changed below, please update the node name and
move this node to top of the soc node.
pcie@fe000000
> + compatible = "rockchip,rk3528-pcie",
> + "rockchip,rk3568-pcie";
> + reg = <0x1 0x40000000 0x0 0x400000>,
We should use the dbi reg area in the 32-bit address space, please use:
reg = <0x0 0xfe000000 0x0 0x400000>,
> + <0x0 0xfe4f0000 0x0 0x10000>,
> + <0x0 0xfc000000 0x0 0x100000>;
> + reg-names = "dbi", "apb", "config";
> + bus-range = <0x0 0xff>;
> + clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
> + <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>,
> + <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE_PHY>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk",
> + "aux", "pipe";
In my U-Boot test I did not have the pipe/phy clock here, do we need it?
With above fixed this more or less matches my U-Boot testing, and is:
Reviewed-by: Jonas Karlman <jonas@xxxxxxxxx>
Regards,
Jonas
> + device_type = "pci";
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "sys", "pmc", "msg", "legacy", "err",
> + "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc 0>,
> + <0 0 0 2 &pcie_intc 1>,
> + <0 0 0 3 &pcie_intc 2>,
> + <0 0 0 4 &pcie_intc 3>;
> + linux,pci-domain = <0>;
> + max-link-speed = <2>;
> + num-lanes = <1>;
> + phys = <&combphy PHY_TYPE_PCIE>;
> + phy-names = "pcie-phy";
> + power-domains = <&power RK3528_PD_VPU>;
> + ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000>,
> + <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000>,
> + <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
> + resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>;
> + reset-names = "pwr", "pipe";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + status = "disabled";
> +
> + pcie_intc: legacy-interrupt-controller {
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> };
> };
>
