On Thu, Sep 11, 2025 at 05:14:51PM +0530, Devendra K Verma wrote:
> AMD MDB IP supports Linked List (LL) mode as well as non-LL mode.
> The current code does not have the mechanisms to enable the
> DMA transactions using the non-LL mode. The following two cases
> are added with this patch:
> - When a valid physical base address is not configured via the
> Xilinx VSEC capability then the IP can still be used in non-LL
> mode. The default mode for all the DMA transactions and for all
> the DMA channels then is non-LL mode.
> - When a valid physical base address is configured but the client
> wants to use the non-LL mode for DMA transactions then also the
> flexibility is provided via the peripheral_config struct member of
> dma_slave_config. In this case the channels can be individually
> configured in non-LL mode. This use case is desirable for single
> DMA transfer of a chunk, this saves the effort of preparing the
> Link List.
> +static pci_bus_addr_t dw_edma_get_phys_addr(struct pci_dev *pdev,
> + struct dw_edma_pcie_data *pdata,
> + enum pci_barno bar)
> +{
> + if (pdev->vendor == PCI_VENDOR_ID_XILINX)
> + return pdata->devmem_phys_off;
> + return pci_bus_address(pdev, bar);
Does this imply that non-Xilinx devices don't have the iATU that
translates a PCI bus address to an internal device address?
> +}
