On 12/09/2025 14:24, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > > The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express > Base Specification 4.0. It is designed for root complex applications and > features a single-lane (x1) implementation. Add documentation for it. > > Tested-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> You cannot really test bindings in that meaning and build tools don't count as testing, just like building C code is not testing, running sparse is not testing, checking with coccinelle is not testing. And it cannot be tested even in the meaning of building, because: > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > --- ... > + interrupt-controller; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ > + <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ > + <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ > + <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ > + clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>, > + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; > + clock-names = "aclk", "pm"; > + resets = <&cpg R9A08G045_PCI_ARESETN>, > + <&cpg R9A08G045_PCI_RST_B>, > + <&cpg R9A08G045_PCI_RST_GP_B>, > + <&cpg R9A08G045_PCI_RST_PS_B>, > + <&cpg R9A08G045_PCI_RST_RSM_B>, > + <&cpg R9A08G045_PCI_RST_CFG_B>, > + <&cpg R9A08G045_PCI_RST_LOAD_B>; > + reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", > + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; > + power-domains = <&cpg>; > + device_type = "pci"; > + #address-cells = <3>; > + #size-cells = <2>; > + max-link-speed = <2>; > + renesas,sysc = <&sysc>; > + status = "disabled"; ...you disabled the example. I don't understand what happened here - why this got now disabled. Code was correct before, but you made so many changes including this one. Best regards, Krzysztof
