On 8/9/25 11:59 AM, Krishna Chaitanya Chundru wrote: > Add PCIe controller and PHY nodes which supports data rates of 8GT/s > and x2 lane. > > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx> > --- [...] > + phys = <&pcie0_phy>; > + phy-names = "pciephy"; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, > + <0x02000000 0 0x60300000 0 0x40300000 0 0x3d00000>; The BAR space is larger (0x2400_0000) please align the overall node style with x1e80100.dtsi Konrad
