This series depend on the sa8775p gcc_aux_clock and link_down reset change https://lore.kernel.org/all/20250725102231.3608298-2-ziyue.zhang@xxxxxxxxxxxxxxxx/ This series adds document, phy, configs support for PCIe in QCS8300. It also adds 'link_down' reset for sa8775p. Have follwing changes: - Add dedicated schema for the PCIe controllers found on QCS8300. - Add compatible for qcs8300 platform. - Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. - Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx> --- Changes in v10: - Update PHY max_items (Johan) - Link to v9: https://lore.kernel.org/all/20250725104037.4054070-1-ziyue.zhang@xxxxxxxxxxxxxxxx/ Changes in v9: - Fix DTB error (Vinod) - Link to v8: https://lore.kernel.org/all/20250714081529.3847385-1-ziyue.zhang@xxxxxxxxxxxxxxxx/ Changes in v8: - rebase sc8280xp-qmp-pcie-phy change to solve conflicts. - Add Fixes tag to phy change (Johan) - Link to v7: https://lore.kernel.org/all/20250625092539.762075-1-quic_ziyuzhan@xxxxxxxxxxx/ Changes in v7: - rebase qcs8300-ride.dtsi change to solve conflicts. - Link to v6: https://lore.kernel.org/all/20250529035635.4162149-1-quic_ziyuzhan@xxxxxxxxxxx/ Changes in v6: - move the qcs8300 and sa8775p phy compatibility entry into the list of PHYs that require six clocks - Update QCS8300 and sa8775p phy dt, remove aux clock. - Fixed compile error found by kernel test robot - Link to v5: https://lore.kernel.org/all/20250507031019.4080541-1-quic_ziyuzhan@xxxxxxxxxxx/ Changes in v5: - Add QCOM PCIe controller version in commit msg (Mani) - Modify platform dts change subject (Dmitry) - Fixed compile error found by kernel test robot - Link to v4: https://lore.kernel.org/linux-phy/20241220055239.2744024-1-quic_ziyuzhan@xxxxxxxxxxx/ Changes in v4: - Add received tag - Fixed compile error found by kernel test robot - Link to v3: https://lore.kernel.org/lkml/202412211301.bQO6vXpo-lkp@xxxxxxxxx/T/#mdd63e5be39acbf879218aef91c87b12d4540e0f7 Changes in v3: - Add received tag(Rob & Dmitry) - Update pcie_phy in gcc node to soc dtsi(Dmitry & Konrad) - remove pcieprot0 node(Konrad & Mani) - Fix format comments(Konrad) - Update base-commit to tag: next-20241213(Bjorn) - Corrected of_device_id.data from 1.9.0 to 1.34.0. - Link to v2: https://lore.kernel.org/all/20241128081056.1361739-1-quic_ziyuzhan@xxxxxxxxxxx/ Changes in v2: - Fix some format comments and match the style in x1e80100(Konrad) - Add global interrupt for PCIe0 and PCIe1(Konrad) - split the soc dtsi and the platform dts into two changes(Konrad) - Link to v1: https://lore.kernel.org/all/20241114095409.2682558-1-quic_ziyuzhan@xxxxxxxxxxx/ Ziyue Zhang (5): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for qcs8300 arm64: dts: qcom: qcs8300: enable pcie0 arm64: dts: qcom: qcs8300-ride: enable pcie0 interface arm64: dts: qcom: qcs8300: enable pcie1 arm64: dts: qcom: qcs8300-ride: enable pcie1 interface .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 17 +- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 80 +++++ arch/arm64/boot/dts/qcom/qcs8300.dtsi | 296 +++++++++++++++++- 3 files changed, 376 insertions(+), 17 deletions(-) base-commit: e2622a23e8405644c7188af39d4c1bd2b405bb27 -- 2.43.0
