Jonathan Cameron wrote: > On Thu, 17 Jul 2025 11:33:54 -0700 > Dan Williams <dan.j.williams@xxxxxxxxx> wrote: > > > PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure, > > enumerates new link capabilities and status added for Gen 6 devices. One > > of the link details enumerated in that register block is the "Segment > > Captured" status in the Device Status 3 register. That status is > > relevant for enabling IDE (Integrity & Data Encryption) whereby > > Selective IDE streams can be limited to a given Requester ID range > > within a given segment. > > > > If a device has captured its Segment value then it knows that PCIe Flit > > Mode is enabled via all links in the path that a configuration write > > traversed. IDE establishment requires that "Segment Base" in > > IDE RID Association Register 2 (PCIe 6.2 Section 7.9.26.5.4.2) be > > programmed if the RID association mechanism is in effect. > > > > When / if IDE + Flit Mode capable devices arrive, the PCI core needs to > > setup the segment base when using the RID association facility, but no > > known deployments today depend on this. > > > > Cc: Lukas Wunner <lukas@xxxxxxxxx> > > Cc: Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx> > > Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > > Cc: Samuel Ortiz <sameo@xxxxxxxxxxxx> > > Cc: Alexey Kardashevskiy <aik@xxxxxxx> > > Cc: Xu Yilun <yilun.xu@xxxxxxxxxxxxxxx> > > Signed-off-by: Dan Williams <dan.j.williams@xxxxxxxxx> > > Reviewed-by: Jonathan Cameron <jonathan.cameron@xxxxxxxxxx> > > > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > index 1b991a88c19c..2d49a4786a9f 100644 > > --- a/include/uapi/linux/pci_regs.h > > +++ b/include/uapi/linux/pci_regs.h > > @@ -751,6 +751,7 @@ > > #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ > > #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ > > #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ > > +#define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */ > > #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */ > > #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */ > > #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT > > @@ -1227,6 +1228,12 @@ > > /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */ > > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE > > > > +/* Device 3 Extended Capability */ > > +#define PCI_DEV3_CAP 0x4 /* Device 3 Capabilities Register */ > > Similar to earlier cases I'd make these 0x04 etc just to copy local style + match spec. Done.
