From: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of
three general-purpose Fabric Interface Controller (FIC) buses that
encapsulate an AXI-M interface. That FIC is responsible for managing
the translations of the upper 32-bits of the AXI-M address. On MPFS,
the Root Port driver needs to take account of that outbound address
translation done by the parent FIC bus before setting up its own
outbound address translation tables. In all cases on MPFS,
the remaining outbound address translation tables are 32-bit only.
Limit the outbound address translation tables to 32-bit only.
Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver")
Signed-off-by: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx>
Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Reviewed-by: Ilpo Jarvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx>
---
This patch was previously part of the linked series here:
https://lore.kernel.org/linux-pci/20241011140043.1250030-2-daire.mcnamara@xxxxxxxxxxxxx/
The rest of the linked series has been applied but we've recently
noticed that this one hasn't been applied.
PolarFire SoC PCIe is currently broken in mainline. Can we get this
fixed up and come up with something cross platform later?
V11:
rebased on mainline
.../pci/controller/plda/pcie-microchip-host.c | 31 ++++++++++++++++---
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c
index 24bbf93b8051..db7a2f8452e5 100644
--- a/drivers/pci/controller/plda/pcie-microchip-host.c
+++ b/drivers/pci/controller/plda/pcie-microchip-host.c
@@ -26,6 +26,8 @@
#include "../pci-host-common.h"
#include "pcie-plda.h"
+#define MC_OUTBOUND_TRANS_TBL_MASK GENMASK(31, 0)
+
#define MC_MAX_NUM_INBOUND_WINDOWS 8
#define MPFS_NC_BOUNCE_ADDR 0x80000000
@@ -700,6 +702,27 @@ static int mc_pcie_setup_inbound_ranges(struct platform_device *pdev,
return 0;
}
+static int mc_pcie_setup_iomems(struct pci_host_bridge *bridge,
+ struct plda_pcie_rp *port)
+{
+ void __iomem *bridge_base_addr = port->bridge_addr;
+ struct resource_entry *entry;
+ u64 pci_addr;
+ u32 index = 1;
+
+ resource_list_for_each_entry(entry, &bridge->windows) {
+ if (resource_type(entry->res) == IORESOURCE_MEM) {
+ pci_addr = entry->res->start - entry->offset;
+ plda_pcie_setup_window(bridge_base_addr, index,
+ entry->res->start & MC_OUTBOUND_TRANS_TBL_MASK,
+ pci_addr, resource_size(entry->res));
+ index++;
+ }
+ }
+
+ return 0;
+}
+
static int mc_platform_init(struct pci_config_window *cfg)
{
struct device *dev = cfg->parent;
@@ -708,15 +731,15 @@ static int mc_platform_init(struct pci_config_window *cfg)
int ret;
/* Configure address translation table 0 for PCIe config space */
- plda_pcie_setup_window(port->bridge_base_addr, 0, cfg->res.start,
- cfg->res.start,
- resource_size(&cfg->res));
+ plda_pcie_setup_window(port->bridge_base_addr, 0,
+ cfg->res.start & MC_OUTBOUND_TRANS_TBL_MASK,
+ 0, resource_size(&cfg->res));
/* Need some fixups in config space */
mc_pcie_enable_msi(port, cfg->win);
/* Configure non-config space outbound ranges */
- ret = plda_pcie_setup_iomems(bridge, &port->plda);
+ ret = mc_pcie_setup_iomems(bridge, &port->plda);
if (ret)
return ret;
--
2.45.2
