On Thu, Jul 31, 2025 at 02:48:23PM +0100, Suzuki K Poulose wrote: > On 31/07/2025 13:17, Jason Gunthorpe wrote: > > On Wed, Jul 30, 2025 at 11:09:35AM +0100, Suzuki K Poulose wrote: > > > > > It is unclear whether devices would need to perform DMA to shared > > > > > (unencrypted) memory while operating in this mode, as TLPs with T=1 > > > > > are generally expected to target private memory. > > > > > > > > PCI SIG supports it, kernel should support it. > > > > > > ACK. On Arm CCA, the device can access shared IPA, with T=1 transaction > > > as long as the mapping is active in the Stage2 managed by RMM. > > > > Right, I expect that the T=0 SMMU S2 translation is a perfect subset of > > the T=1 S2 rmm translation. At most pages that are not available to > > T=0 should be removed when making the subset. > > Yes, this is what the VMM is supposed to do today, see [0] & [1]. Okay great! > > I'm not sure what the plan is here on ARM though, do you expect to > > pre-load the entire T=0 SMMU S2 with the shared IPA aliases and rely > > on the GPT for protection or will the hypervisor dynamically change > > the T=0 SMMU S2 after each shared/private change? Same question for > > Yes, share/private transitions do go all the way back to VMM and it > is supposed to make the necessary changes to the SMMU S2 (as in [1]). Okay, it works, but also why?
