This series drop gcc_aux_clock in pcie phy, the pcie aux clock should be gcc_phy_aux_clock. And sa8775p platform support link_down reset in hardware, so add it for both pcie0 and pcie1 to provide a better user experience. Have follwing changes: - Update pcie phy bindings for sa8775p. - Document link_down reset. - Remove aux clock from pcie phy. - Add link_down reset for pcie. Signed-off-by: Ziyue Zhang <quic_ziyuzhan@xxxxxxxxxxx> Changes in v7: - Fixed rebase confict - Link to v6: https://lore.kernel.org/all/20250725095302.3408875-1-ziyue.zhang@xxxxxxxxxxxxxxxx/ Changes in v6: - Update phy bindings commit msg(Johan) - Add Acked-by tag - Link to v5: https://lore.kernel.org/all/20250718081718.390790-1-ziyue.zhang@xxxxxxxxxxxxxxxx/ Changes in v5: - Update phy bindings(Johan) - Link to v4: https://lore.kernel.org/all/20250718071207.160988-1-ziyue.zhang@xxxxxxxxxxxxxxxx/ Changes in v4: - Update phy bindings, and commit msg(Johan) - Add ABI break commit msg - Link to v3: https://lore.kernel.org/linux-arm-msm/20250625090048.624399-1-quic_ziyuzhan@xxxxxxxxxxx/ Changes in v3: - Update phy bindings, remove phy_aux clock (Johan) - Update DT binding's description (Johan) - Link to v2: https://lore.kernel.org/all/20250617021617.2793902-1-quic_ziyuzhan@xxxxxxxxxxx/ Changes in v2: - Change link_down reset from optional to mandatory(Konrad) - Link to v1: https://lore.kernel.org/all/20250529035416.4159963-1-quic_ziyuzhan@xxxxxxxxxxx/ Ziyue Zhang (3): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings arm64: dts: qcom: sa8775p: remove aux clock from pcie phy arm64: dts: qcom: sa8775p: add link_down reset for pcie .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 4 +- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 42 ++++++++++++------- 2 files changed, 28 insertions(+), 18 deletions(-) base-commit: d7af19298454ed155f5cf67201a70f5cf836c842 -- 2.34.1
